diff options
| author | Nagabhushana Netagunte <nagabhushana.netagunte@ti.com> | 2011-09-03 22:21:04 -0400 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2011-09-04 11:36:19 +0200 |
| commit | 0f3d6b06ea06e5b0295e4a8222a25bc95a70c026 (patch) | |
| tree | 91a2566d7d9f01c2920e00042d77a7364e40fd28 /arch/arm/include/asm/arch-davinci/hardware.h | |
| parent | ba511f779a584f77b4b798fc40685bfe8d3d5163 (diff) | |
da850: modifications for Logic PD Rev.3 AM18xx EVM
AHCLKR/UART1_RTS/GP0[11] pin needs to be configured for
NOR to work on Rev.3 EVM. When GP0[11] is low,
the SD0 interface will not work, but NOR flash will.
Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Diffstat (limited to 'arch/arm/include/asm/arch-davinci/hardware.h')
| -rw-r--r-- | arch/arm/include/asm/arch-davinci/hardware.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index 4a3af7d3b6..692d50755a 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -159,6 +159,10 @@ typedef volatile unsigned int * dv_reg_p; #define HOST1CFG (DAVINCI_BOOTCFG_BASE + 0x44) #define PSC0_MDCTL (DAVINCI_PSC0_BASE + 0xa00) +#define GPIO_BANK0_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x10) +#define GPIO_BANK0_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x14) +#define GPIO_BANK0_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x18) +#define GPIO_BANK0_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x1c) #define GPIO_BANK2_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x38) #define GPIO_BANK2_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x3c) #define GPIO_BANK2_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x40) |