diff options
| author | Rajeshwari Birje <rajeshwari.s@samsung.com> | 2013-12-26 09:44:22 +0530 |
|---|---|---|
| committer | Minkyu Kang <mk7.kang@samsung.com> | 2013-12-30 16:50:34 +0900 |
| commit | f3d7c2fe9da9b03230cecd634ddbbb2654f3d13d (patch) | |
| tree | 43c82f06ad8dd72436659a989ce641e6dd7c385b /arch/arm/include/asm/arch-exynos/dmc.h | |
| parent | 060c227a2861b0702e34eabe08eea9cc5bb68b45 (diff) | |
Exynos5420: Add DDR3 initialization for 5420
This patch intends to add DDR3 initialization code for Exynos5420.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'arch/arm/include/asm/arch-exynos/dmc.h')
| -rw-r--r-- | arch/arm/include/asm/arch-exynos/dmc.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-exynos/dmc.h b/arch/arm/include/asm/arch-exynos/dmc.h index 32ad3aeab1..d78536d2df 100644 --- a/arch/arm/include/asm/arch-exynos/dmc.h +++ b/arch/arm/include/asm/arch-exynos/dmc.h @@ -419,6 +419,15 @@ struct exynos5420_phy_control { unsigned int phy_con42; }; +struct exynos5420_tzasc { + unsigned char res1[0xf00]; + unsigned int membaseconfig0; + unsigned int membaseconfig1; + unsigned char res2[0x8]; + unsigned int memconfig0; + unsigned int memconfig1; +}; + enum ddr_mode { DDR_MODE_DDR2, DDR_MODE_DDR3, @@ -453,6 +462,7 @@ enum mem_manuf { #define PHY_CON0_T_WRRDCMD_SHIFT 17 #define PHY_CON0_T_WRRDCMD_MASK (0x7 << PHY_CON0_T_WRRDCMD_SHIFT) #define PHY_CON0_CTRL_DDR_MODE_SHIFT 11 +#define PHY_CON0_CTRL_DDR_MODE_MASK 0x3 /* PHY_CON1 register fields */ #define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT 0 |