diff options
| author | Inderpal Singh <chander.kashyap@linaro.org> | 2014-01-08 09:19:56 +0530 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2014-01-13 12:23:28 +0100 |
| commit | 16f9480dfcac19f59fe9d7896b2af3bcbfc78f23 (patch) | |
| tree | 7ee66d2a753a5953d4f441c317c0888e0fb412c0 /arch/arm/include/asm/arch-exynos/ehci.h | |
| parent | dcad280056b656896a18c5955d8facc236a1bed7 (diff) | |
usb: ehci: exynos: set/reset hsic phys
The controller has 3 ports. The port0 is for USB 2.0 Phy, port1 and port2
are for HSIC phys. The usb 2.0 phy is already being setup. This patch
sets up the hsic phys.
Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org>
Diffstat (limited to 'arch/arm/include/asm/arch-exynos/ehci.h')
| -rw-r--r-- | arch/arm/include/asm/arch-exynos/ehci.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-exynos/ehci.h b/arch/arm/include/asm/arch-exynos/ehci.h index d79f25c0c3..d2d70bd82b 100644 --- a/arch/arm/include/asm/arch-exynos/ehci.h +++ b/arch/arm/include/asm/arch-exynos/ehci.h @@ -29,6 +29,20 @@ #define EHCICTRL_ENAINCR8 (1 << 27) #define EHCICTRL_ENAINCR16 (1 << 26) +#define HSIC_CTRL_REFCLKSEL (0x2) +#define HSIC_CTRL_REFCLKSEL_MASK (0x3) +#define HSIC_CTRL_REFCLKSEL_SHIFT (23) + +#define HSIC_CTRL_REFCLKDIV_12 (0x24) +#define HSIC_CTRL_REFCLKDIV_MASK (0x7f) +#define HSIC_CTRL_REFCLKDIV_SHIFT (16) + +#define HSIC_CTRL_SIDDQ (0x1 << 6) +#define HSIC_CTRL_FORCESLEEP (0x1 << 5) +#define HSIC_CTRL_FORCESUSPEND (0x1 << 4) +#define HSIC_CTRL_UTMISWRST (0x1 << 2) +#define HSIC_CTRL_PHYSWRST (0x1 << 0) + /* Register map for PHY control */ struct exynos_usb_phy { unsigned int usbphyctrl0; |