armv8: lx2160a: Add LX2160A SoC Support

LX2160A Soc is based on Layerscape Chassis Generation 3.2
architecture with features:
 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC,
 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers,
 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs,
 4 TZASC instances, etc.

SoC personalites:
LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs
LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs

Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

1 files changed, 56 insertions, 0 deletions

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index bd4ca88e16..d4f80a24cd 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
+ * Copyright 2016-2018 NXP
  * Copyright 2015, Freescale Semiconductor
  */
 
@@ -176,6 +177,61 @@
 #define SYS_FSL_OCRAM_SPACE_SIZE	0x00200000 /* 2M space */
 #define CONFIG_SYS_FSL_OCRAM_SIZE	0x00020000 /* Real size 128K */
 
+/* LX2160A Soc Support */
+#elif defined(CONFIG_ARCH_LX2160A)
+#define TZPC_BASE				0x02200000
+#define TZPCDECPROT_0_SET_BASE			(TZPC_BASE + 0x804)
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_EARLY_INIT
+#define SRDS_MAX_LANES  8
+#ifndef L1_CACHE_BYTES
+#define L1_CACHE_SHIFT		6
+#define L1_CACHE_BYTES		BIT(L1_CACHE_SHIFT)
+#endif
+#define CONFIG_SYS_FSL_CORES_PER_CLUSTER	2
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1, 1, 1, 4, 4, 4, 4 }
+#define CONFIG_SYS_FSL_NUM_CC_PLLS		4
+
+#define CONFIG_SYS_PAGE_SIZE			0x10000
+
+#define CONFIG_SYS_FSL_OCRAM_BASE		0x18000000 /* initial RAM */
+#define SYS_FSL_OCRAM_SPACE_SIZE		0x00200000 /* 2M space */
+#define CONFIG_SYS_FSL_OCRAM_SIZE		0x00040000 /* Real size 256K */
+
+/* DDR */
+#define CONFIG_SYS_DDR_BLOCK1_SIZE		((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED			CONFIG_SYS_DDR_BLOCK1_SIZE
+
+#define CONFIG_SYS_FSL_CCSR_GUR_LE
+#define CONFIG_SYS_FSL_CCSR_SCFG_LE
+#define CONFIG_SYS_FSL_ESDHC_LE
+#define CONFIG_SYS_FSL_PEX_LUT_LE
+
+#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE				0x06000000
+#define GICR_BASE				0x06200000
+
+/* SMMU Definitions */
+#define SMMU_BASE				0x05000000 /* GR0 Base */
+
+/* SFP */
+#define CONFIG_SYS_FSL_SFP_VER_3_4
+#define CONFIG_SYS_FSL_SFP_LE
+#define CONFIG_SYS_FSL_SRK_LE
+
+/* Security Monitor */
+#define CONFIG_SYS_FSL_SEC_MON_LE
+
+/* Secure Boot */
+#define CONFIG_ESBC_HDR_LS
+
+/* DCFG - GUR */
+#define CONFIG_SYS_FSL_CCSR_GUR_LE
+
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
+
 #elif defined(CONFIG_FSL_LSCH2)
 #define CONFIG_SYS_FSL_OCRAM_BASE		0x10000000 /* initial RAM */
 #define SYS_FSL_OCRAM_SPACE_SIZE		0x00200000 /* 2M space */