diff options
| author | Rajesh Bhagat <rajesh.bhagat@nxp.com> | 2018-01-17 16:13:00 +0530 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2018-01-23 11:18:12 -0800 |
| commit | a1f95ff7d7bae4d4dac59aa6d53f3625af43765e (patch) | |
| tree | d975cb046e2fab6fb8aa8c25049744c7ffd85484 /arch/arm/include/asm/arch-fsl-layerscape/soc.h | |
| parent | 485c13c7536731991c59f7b3432bc33c9dafb0f0 (diff) | |
armv8: lsch3: Add serdes and DDR voltage setup
Adds SERDES voltage and reset SERDES lanes API and makes
enable/disable DDR controller support 0.9V API common.
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/include/asm/arch-fsl-layerscape/soc.h')
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/soc.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 1e65e4e114..cb760b5b38 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -121,6 +121,7 @@ struct ccsr_ahci { #ifdef CONFIG_FSL_LSCH3 void fsl_lsch3_early_init_f(void); +int get_core_volt_from_fuse(void); #elif defined(CONFIG_FSL_LSCH2) void fsl_lsch2_early_init_f(void); int setup_chip_volt(void); |