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| author | Laurentiu Tudor <laurentiu.tudor@nxp.com> | 2019-07-30 17:29:57 +0300 |
|---|---|---|
| committer | Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | 2019-08-22 09:07:36 +0530 |
| commit | aef654a2ed386d8bd53053383f6bf15ba016a79c (patch) | |
| tree | 7dcfb1c5f8418120183dba9542a29eb74cb5f9e8 /arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h | |
| parent | 08f9bc9f4332e13a4ba4705d84d62e41a45b3fbe (diff) | |
armv8: fsl-layerscape: make icid setup endianness aware
The current implementation assumes that the registers holding the ICIDs
are universally big endian. That's no longer the case on newer
platforms so update the code to take into account the endianness of
each register.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Diffstat (limited to 'arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h')
0 files changed, 0 insertions, 0 deletions