diff options
| author | Yangbo Lu <yangbo.lu@nxp.com> | 2019-05-23 11:05:45 +0800 |
|---|---|---|
| committer | Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | 2019-06-19 12:54:56 +0530 |
| commit | 087bfe67ac2555c37b257335424b7c193d7f6afd (patch) | |
| tree | 9b302a808543434d4457483f27f63caf97d1a5be /arch/arm/include/asm/arch-fsl-layerscape | |
| parent | d17eb57dcf4cc6b2624327563d85fb8e99a0ae4f (diff) | |
armv8: fsl-lsch3: add clock support for the second eSDHC
Layerscape began to use two eSDHC controllers, for example,
LS1028A. They are same IP block with same reference clock.
This patch is to add clock support for the second eSDHC.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Diffstat (limited to 'arch/arm/include/asm/arch-fsl-layerscape')
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/clock.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/clock.h b/arch/arm/include/asm/arch-fsl-layerscape/clock.h index cf058d22a9..b37a08d265 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/clock.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/clock.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2019 NXP Semiconductors * */ @@ -14,6 +15,7 @@ enum mxc_clock { MXC_BUS_CLK, MXC_UART_CLK, MXC_ESDHC_CLK, + MXC_ESDHC2_CLK, MXC_I2C_CLK, MXC_DSPI_CLK, }; |