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authorPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>2016-01-25 12:08:45 +0530
committerYork Sun <york.sun@nxp.com>2016-03-21 12:42:10 -0700
commit2b690b9837b4bb6d3598e4259581e399d078bff8 (patch)
tree064ef4d062fc75af9475cb1a2a4f36e713883fd5 /arch/arm/include/asm/arch-fsl-layerscape
parentc05016ab0b122b28395f0532e6447e5ec2705fe9 (diff)
armv8: lsch3: Enable WUO config for RNI-20 node
Enable wuo config to accelerate coherent ordered writes for LS2080A and LS2085A. WRIOP IP is connected to RNI-20 Node. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/include/asm/arch-fsl-layerscape')
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/config.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 0ef7c9dd95..22f9c8fd65 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -91,6 +91,8 @@
#define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110)
#define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210)
+#define CCI_AUX_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x0500)
+
/* TZ Protection Controller Definitions */
#define TZPC_BASE 0x02200000
#define TZPCR0SIZE_BASE (TZPC_BASE)