Move architecture-specific includes to arch/$ARCH/include/asm

This helps to clean up the include/ directory so that it only contains
non-architecture-specific headers and also matches Linux's directory
layout which many U-Boot developers are already familiar with.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>

2 files changed, 855 insertions, 0 deletions

diff --git a/arch/arm/include/asm/arch-ixp/ixp425.h b/arch/arm/include/asm/arch-ixp/ixp425.h
new file mode 100644
index 0000000000..2114437dc7
--- /dev/null
+++ b/arch/arm/include/asm/arch-ixp/ixp425.h
@@ -0,0 +1,543 @@
+/*
+ * include/asm-arm/arch-ixp425/ixp425.h
+ *
+ * Register definitions for IXP425
+ *
+ * Copyright (C) 2002 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef _ASM_ARM_IXP425_H_
+#define _ASM_ARM_IXP425_H_
+
+#define BIT(x)	(1<<(x))
+
+/* FIXME: Only this does work for u-boot... find out why... [RS] */
+#define UBOOT_REG_FIX 1
+#ifdef UBOOT_REG_FIX
+# undef	io_p2v
+# undef __REG
+# ifndef __ASSEMBLY__
+#  define io_p2v(PhAdd)    (PhAdd)
+#  define __REG(x)	(*((volatile u32 *)io_p2v(x)))
+#  define __REG2(x,y)	(*(volatile u32 *)((u32)&__REG(x) + (y)))
+# else
+#  define __REG(x) (x)
+# endif
+#endif /* UBOOT_REG_FIX */
+
+/*
+ *
+ * IXP425 Memory map:
+ *
+ * Phy		Phy Size	Map Size	Virt		Description
+ * =========================================================================
+ *
+ * 0x00000000	0x10000000					SDRAM 1
+ *
+ * 0x10000000	0x10000000					SDRAM 2
+ *
+ * 0x20000000	0x10000000					SDRAM 3
+ *
+ * 0x30000000	0x10000000					SDRAM 4
+ *
+ * The above four are aliases to the same memory location  (0x00000000)
+ *
+ * 0x48000000	 0x4000000					PCI Memory
+ *
+ * 0x50000000	0x10000000			Not Mapped	EXP BUS
+ *
+ * 0x6000000	0x00004000	    0x4000	0xFFFEB000	QMgr
+ *
+ * 0xC0000000	     0x100	    0x1000	0xFFFDD000	PCI CFG
+ *
+ * 0xC4000000	     0x100          0x1000	0xFFFDE000	EXP CFG
+ *
+ * 0xC8000000	    0xC000          0xC000	0xFFFDF000	PERIPHERAL
+ *
+ * 0xCC000000	     0x100	    0x1000	Not Mapped	SDRAM CFG
+ */
+
+/*
+ * SDRAM
+ */
+#define IXP425_SDRAM_BASE		(0x00000000)
+#define IXP425_SDRAM_BASE_ALT		(0x10000000)
+
+
+/*
+ * PCI Configuration space
+ */
+#define IXP425_PCI_CFG_BASE_PHYS	(0xC0000000)
+#define IXP425_PCI_CFG_REGION_SIZE	(0x00001000)
+
+/*
+ * Expansion BUS Configuration registers
+ */
+#define IXP425_EXP_CFG_BASE_PHYS	(0xC4000000)
+#define IXP425_EXP_CFG_REGION_SIZE	(0x00001000)
+
+/*
+ * Peripheral space
+ */
+#define IXP425_PERIPHERAL_BASE_PHYS	(0xC8000000)
+#define IXP425_PERIPHERAL_REGION_SIZE	(0x0000C000)
+
+/*
+ * SDRAM configuration registers
+ */
+#define IXP425_SDRAM_CFG_BASE_PHYS	(0xCC000000)
+
+/*
+ * Q Manager space .. not static mapped
+ */
+#define IXP425_QMGR_BASE_PHYS		(0x60000000)
+#define IXP425_QMGR_REGION_SIZE		(0x00004000)
+
+/*
+ * Expansion BUS
+ *
+ * Expansion Bus 'lives' at either base1 or base 2 depending on the value of
+ * Exp Bus config registers:
+ *
+ * Setting bit 31 of IXP425_EXP_CFG0 puts SDRAM at zero,
+ * and The expansion bus to IXP425_EXP_BUS_BASE2
+ */
+#define IXP425_EXP_BUS_BASE1_PHYS	(0x00000000)
+#define IXP425_EXP_BUS_BASE2_PHYS	(0x50000000)
+
+#define IXP425_EXP_BUS_BASE_PHYS	IXP425_EXP_BUS_BASE2_PHYS
+
+#define IXP425_EXP_BUS_REGION_SIZE	(0x08000000)
+#define IXP425_EXP_BUS_CSX_REGION_SIZE	(0x01000000)
+
+#define IXP425_EXP_BUS_CS0_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x00000000)
+#define IXP425_EXP_BUS_CS1_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x01000000)
+#define IXP425_EXP_BUS_CS2_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x02000000)
+#define IXP425_EXP_BUS_CS3_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x03000000)
+#define IXP425_EXP_BUS_CS4_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x04000000)
+#define IXP425_EXP_BUS_CS5_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x05000000)
+#define IXP425_EXP_BUS_CS6_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x06000000)
+#define IXP425_EXP_BUS_CS7_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x07000000)
+
+#define IXP425_FLASH_WRITABLE	(0x2)
+#define IXP425_FLASH_DEFAULT	(0xbcd23c40)
+#define IXP425_FLASH_WRITE	(0xbcd23c42)
+
+#define IXP425_EXP_CS0_OFFSET	0x00
+#define IXP425_EXP_CS1_OFFSET   0x04
+#define IXP425_EXP_CS2_OFFSET   0x08
+#define IXP425_EXP_CS3_OFFSET   0x0C
+#define IXP425_EXP_CS4_OFFSET   0x10
+#define IXP425_EXP_CS5_OFFSET   0x14
+#define IXP425_EXP_CS6_OFFSET   0x18
+#define IXP425_EXP_CS7_OFFSET   0x1C
+#define IXP425_EXP_CFG0_OFFSET	0x20
+#define IXP425_EXP_CFG1_OFFSET	0x24
+#define IXP425_EXP_CFG2_OFFSET	0x28
+#define IXP425_EXP_CFG3_OFFSET	0x2C
+
+/*
+ * Expansion Bus Controller registers.
+ */
+#ifndef __ASSEMBLY__
+#define IXP425_EXP_REG(x) ((volatile u32 *)(IXP425_EXP_CFG_BASE_PHYS+(x)))
+#else
+#define IXP425_EXP_REG(x) (IXP425_EXP_CFG_BASE_PHYS+(x))
+#endif
+
+#define IXP425_EXP_CS0      IXP425_EXP_REG(IXP425_EXP_CS0_OFFSET)
+#define IXP425_EXP_CS1      IXP425_EXP_REG(IXP425_EXP_CS1_OFFSET)
+#define IXP425_EXP_CS2      IXP425_EXP_REG(IXP425_EXP_CS2_OFFSET)
+#define IXP425_EXP_CS3      IXP425_EXP_REG(IXP425_EXP_CS3_OFFSET)
+#define IXP425_EXP_CS4      IXP425_EXP_REG(IXP425_EXP_CS4_OFFSET)
+#define IXP425_EXP_CS5      IXP425_EXP_REG(IXP425_EXP_CS5_OFFSET)
+#define IXP425_EXP_CS6      IXP425_EXP_REG(IXP425_EXP_CS6_OFFSET)
+#define IXP425_EXP_CS7      IXP425_EXP_REG(IXP425_EXP_CS7_OFFSET)
+
+#define IXP425_EXP_CFG0     IXP425_EXP_REG(IXP425_EXP_CFG0_OFFSET)
+#define IXP425_EXP_CFG1     IXP425_EXP_REG(IXP425_EXP_CFG1_OFFSET)
+#define IXP425_EXP_CFG2     IXP425_EXP_REG(IXP425_EXP_CFG2_OFFSET)
+#define IXP425_EXP_CFG3     IXP425_EXP_REG(IXP425_EXP_CFG3_OFFSET)
+
+/*
+ * SDRAM Controller registers.
+ */
+#define IXP425_SDR_CONFIG_OFFSET	0x00
+#define IXP425_SDR_REFRESH_OFFSET	0x04
+#define IXP425_SDR_IR_OFFSET		0x08
+
+#define IXP425_SDRAM_REG(x)	(IXP425_SDRAM_CFG_BASE_PHYS+(x))
+
+#define IXP425_SDR_CONFIG	IXP425_SDRAM_REG(IXP425_SDR_CONFIG_OFFSET)
+#define IXP425_SDR_REFRESH	IXP425_SDRAM_REG(IXP425_SDR_REFRESH_OFFSET)
+#define IXP425_SDR_IR		IXP425_SDRAM_REG(IXP425_SDR_IR_OFFSET)
+
+/*
+ * UART registers
+ */
+#define IXP425_UART1		0
+#define IXP425_UART2		0x1000
+
+#define IXP425_UART_RBR_OFFSET	0x00
+#define IXP425_UART_THR_OFFSET	0x00
+#define IXP425_UART_DLL_OFFSET	0x00
+#define IXP425_UART_IER_OFFSET	0x04
+#define IXP425_UART_DLH_OFFSET	0x04
+#define IXP425_UART_IIR_OFFSET	0x08
+#define IXP425_UART_FCR_OFFSET	0x00
+#define IXP425_UART_LCR_OFFSET	0x0c
+#define IXP425_UART_MCR_OFFSET	0x10
+#define IXP425_UART_LSR_OFFSET	0x14
+#define IXP425_UART_MSR_OFFSET	0x18
+#define IXP425_UART_SPR_OFFSET	0x1c
+#define IXP425_UART_ISR_OFFSET	0x20
+
+#define IXP425_UART_CFG_BASE_PHYS	(0xc8000000)
+
+#define RBR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_RBR_OFFSET)
+#define THR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_THR_OFFSET)
+#define DLL(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_DLL_OFFSET)
+#define IER(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_IER_OFFSET)
+#define DLH(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_DLH_OFFSET)
+#define IIR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_IIR_OFFSET)
+#define FCR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_FCR_OFFSET)
+#define LCR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_LCR_OFFSET)
+#define MCR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_MCR_OFFSET)
+#define LSR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_LSR_OFFSET)
+#define MSR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_MSR_OFFSET)
+#define SPR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_SPR_OFFSET)
+#define ISR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_ISR_OFFSET)
+
+#define IER_DMAE	(1 << 7)	/* DMA Requests Enable */
+#define IER_UUE		(1 << 6)	/* UART Unit Enable */
+#define IER_NRZE	(1 << 5)	/* NRZ coding Enable */
+#define IER_RTIOE	(1 << 4)	/* Receiver Time Out Interrupt Enable */
+#define IER_MIE		(1 << 3)	/* Modem Interrupt Enable */
+#define IER_RLSE	(1 << 2)	/* Receiver Line Status Interrupt Enable */
+#define IER_TIE		(1 << 1)	/* Transmit Data request Interrupt Enable */
+#define IER_RAVIE	(1 << 0)	/* Receiver Data Available Interrupt Enable */
+
+#define IIR_FIFOES1	(1 << 7)	/* FIFO Mode Enable Status */
+#define IIR_FIFOES0	(1 << 6)	/* FIFO Mode Enable Status */
+#define IIR_TOD		(1 << 3)	/* Time Out Detected */
+#define IIR_IID2	(1 << 2)	/* Interrupt Source Encoded */
+#define IIR_IID1	(1 << 1)	/* Interrupt Source Encoded */
+#define IIR_IP		(1 << 0)	/* Interrupt Pending (active low) */
+
+#define FCR_ITL2	(1 << 7)	/* Interrupt Trigger Level */
+#define FCR_ITL1	(1 << 6)	/* Interrupt Trigger Level */
+#define FCR_RESETTF	(1 << 2)	/* Reset Transmitter FIFO */
+#define FCR_RESETRF	(1 << 1)	/* Reset Receiver FIFO */
+#define FCR_TRFIFOE	(1 << 0)	/* Transmit and Receive FIFO Enable */
+#define FCR_ITL_1	(0)
+#define FCR_ITL_8	(FCR_ITL1)
+#define FCR_ITL_16	(FCR_ITL2)
+#define FCR_ITL_32	(FCR_ITL2|FCR_ITL1)
+
+#define LCR_DLAB	(1 << 7)	/* Divisor Latch Access Bit */
+#define LCR_SB		(1 << 6)	/* Set Break */
+#define LCR_STKYP	(1 << 5)	/* Sticky Parity */
+#define LCR_EPS		(1 << 4)	/* Even Parity Select */
+#define LCR_PEN		(1 << 3)	/* Parity Enable */
+#define LCR_STB		(1 << 2)	/* Stop Bit */
+#define LCR_WLS1	(1 << 1)	/* Word Length Select */
+#define LCR_WLS0	(1 << 0)	/* Word Length Select */
+
+#define LSR_FIFOE	(1 << 7)	/* FIFO Error Status */
+#define LSR_TEMT	(1 << 6)	/* Transmitter Empty */
+#define LSR_TDRQ	(1 << 5)	/* Transmit Data Request */
+#define LSR_BI		(1 << 4)	/* Break Interrupt */
+#define LSR_FE		(1 << 3)	/* Framing Error */
+#define LSR_PE		(1 << 2)	/* Parity Error */
+#define LSR_OE		(1 << 1)	/* Overrun Error */
+#define LSR_DR		(1 << 0)	/* Data Ready */
+
+#define MCR_LOOP	(1 << 4)	*/
+#define MCR_OUT2	(1 << 3)	/* force MSR_DCD in loopback mode */
+#define MCR_OUT1	(1 << 2)	/* force MSR_RI in loopback mode */
+#define MCR_RTS		(1 << 1)	/* Request to Send */
+#define MCR_DTR		(1 << 0)	/* Data Terminal Ready */
+
+#define MSR_DCD		(1 << 7)	/* Data Carrier Detect */
+#define MSR_RI		(1 << 6)	/* Ring Indicator */
+#define MSR_DSR		(1 << 5)	/* Data Set Ready */
+#define MSR_CTS		(1 << 4)	/* Clear To Send */
+#define MSR_DDCD	(1 << 3)	/* Delta Data Carrier Detect */
+#define MSR_TERI	(1 << 2)	/* Trailing Edge Ring Indicator */
+#define MSR_DDSR	(1 << 1)	/* Delta Data Set Ready */
+#define MSR_DCTS	(1 << 0)	/* Delta Clear To Send */
+
+#define IXP425_CONSOLE_UART_BASE_PHYS IXP425_UART1_BASE_PHYS
+/*
+ * Peripheral Space Registers
+ */
+#define IXP425_UART1_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x0000)
+#define IXP425_UART2_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x1000)
+#define IXP425_PMU_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x2000)
+#define IXP425_INTC_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x3000)
+#define IXP425_GPIO_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x4000)
+#define IXP425_TIMER_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x5000)
+#define IXP425_NPEA_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x6000)
+#define IXP425_NPEB_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x7000)
+#define IXP425_NPEC_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x8000)
+#define IXP425_EthA_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x9000)
+#define IXP425_EthB_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0xA000)
+#define IXP425_USB_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0xB000)
+
+/*
+ * UART Register Definitions , Offsets only as there are 2 UARTS.
+ *   IXP425_UART1_BASE , IXP425_UART2_BASE.
+ */
+
+#undef  UART_NO_RX_INTERRUPT
+
+#define IXP425_UART_XTAL        14745600
+
+/*
+ * Constants to make it easy to access  Interrupt Controller registers
+ */
+#define IXP425_ICPR_OFFSET	0x00 /* Interrupt Status */
+#define IXP425_ICMR_OFFSET	0x04 /* Interrupt Enable */
+#define IXP425_ICLR_OFFSET	0x08 /* Interrupt IRQ/FIQ Select */
+#define IXP425_ICIP_OFFSET      0x0C /* IRQ Status */
+#define IXP425_ICFP_OFFSET	0x10 /* FIQ Status */
+#define IXP425_ICHR_OFFSET	0x14 /* Interrupt Priority */
+#define IXP425_ICIH_OFFSET	0x18 /* IRQ Highest Pri Int */
+#define IXP425_ICFH_OFFSET	0x1C /* FIQ Highest Pri Int */
+
+#define N_IRQS			32
+#define IXP425_TIMER_2_IRQ	11
+
+/*
+ * Interrupt Controller Register Definitions.
+ */
+#ifndef __ASSEMBLY__
+#define IXP425_INTC_REG(x) ((volatile u32 *)(IXP425_INTC_BASE_PHYS+(x)))
+#else
+#define IXP425_INTC_REG(x) (IXP425_INTC_BASE_PHYS+(x))
+#endif
+
+#define IXP425_ICPR     IXP425_INTC_REG(IXP425_ICPR_OFFSET)
+#define IXP425_ICMR     IXP425_INTC_REG(IXP425_ICMR_OFFSET)
+#define IXP425_ICLR     IXP425_INTC_REG(IXP425_ICLR_OFFSET)
+#define IXP425_ICIP     IXP425_INTC_REG(IXP425_ICIP_OFFSET)
+#define IXP425_ICFP     IXP425_INTC_REG(IXP425_ICFP_OFFSET)
+#define IXP425_ICHR     IXP425_INTC_REG(IXP425_ICHR_OFFSET)
+#define IXP425_ICIH     IXP425_INTC_REG(IXP425_ICIH_OFFSET)
+#define IXP425_ICFH     IXP425_INTC_REG(IXP425_ICFH_OFFSET)
+
+/*
+ * Constants to make it easy to access GPIO registers
+ */
+#define IXP425_GPIO_GPOUTR_OFFSET       0x00
+#define IXP425_GPIO_GPOER_OFFSET        0x04
+#define IXP425_GPIO_GPINR_OFFSET        0x08
+#define IXP425_GPIO_GPISR_OFFSET        0x0C
+#define IXP425_GPIO_GPIT1R_OFFSET	0x10
+#define IXP425_GPIO_GPIT2R_OFFSET	0x14
+#define IXP425_GPIO_GPCLKR_OFFSET	0x18
+#define IXP425_GPIO_GPDBSELR_OFFSET	0x1C
+
+/*
+ * GPIO Register Definitions.
+ * [Only perform 32bit reads/writes]
+ */
+#define IXP425_GPIO_REG(x) ((volatile u32 *)(IXP425_GPIO_BASE_PHYS+(x)))
+
+#define IXP425_GPIO_GPOUTR	IXP425_GPIO_REG(IXP425_GPIO_GPOUTR_OFFSET)
+#define IXP425_GPIO_GPOER       IXP425_GPIO_REG(IXP425_GPIO_GPOER_OFFSET)
+#define IXP425_GPIO_GPINR       IXP425_GPIO_REG(IXP425_GPIO_GPINR_OFFSET)
+#define IXP425_GPIO_GPISR       IXP425_GPIO_REG(IXP425_GPIO_GPISR_OFFSET)
+#define IXP425_GPIO_GPIT1R      IXP425_GPIO_REG(IXP425_GPIO_GPIT1R_OFFSET)
+#define IXP425_GPIO_GPIT2R      IXP425_GPIO_REG(IXP425_GPIO_GPIT2R_OFFSET)
+#define IXP425_GPIO_GPCLKR      IXP425_GPIO_REG(IXP425_GPIO_GPCLKR_OFFSET)
+#define IXP425_GPIO_GPDBSELR    IXP425_GPIO_REG(IXP425_GPIO_GPDBSELR_OFFSET)
+
+/*
+ * Macros to make it easy to access the GPIO registers
+ */
+#define GPIO_OUTPUT_ENABLE(line)	*IXP425_GPIO_GPOER &= ~(1 << (line))
+#define GPIO_OUTPUT_DISABLE(line)	*IXP425_GPIO_GPOER |= (1 << (line))
+#define GPIO_OUTPUT_SET(line)		*IXP425_GPIO_GPOUTR |= (1 << (line))
+#define GPIO_OUTPUT_CLEAR(line)		*IXP425_GPIO_GPOUTR &= ~(1 << (line))
+#define GPIO_INT_ACT_LOW_SET(line)	*IXP425_GPIO_GPIT1R = \
+		(*IXP425_GPIO_GPIT1R & ~(0x7 << (line * 3))) | (0x1 << (line * 3))
+
+/*
+ * Constants to make it easy to access Timer Control/Status registers
+ */
+#define IXP425_OSTS_OFFSET	0x00  /* Continious TimeStamp */
+#define IXP425_OST1_OFFSET	0x04  /* Timer 1 Timestamp */
+#define IXP425_OSRT1_OFFSET	0x08  /* Timer 1 Reload */
+#define IXP425_OST2_OFFSET	0x0C  /* Timer 2 Timestamp */
+#define IXP425_OSRT2_OFFSET	0x10  /* Timer 2 Reload */
+#define IXP425_OSWT_OFFSET	0x14  /* Watchdog Timer */
+#define IXP425_OSWE_OFFSET	0x18  /* Watchdog Enable */
+#define IXP425_OSWK_OFFSET	0x1C  /* Watchdog Key */
+#define IXP425_OSST_OFFSET	0x20  /* Timer Status */
+
+/*
+ * Operating System Timer Register Definitions.
+ */
+
+#ifndef __ASSEMBLY__
+#define IXP425_TIMER_REG(x) ((volatile u32 *)(IXP425_TIMER_BASE_PHYS+(x)))
+#else
+#define IXP425_TIMER_REG(x) (IXP425_TIMER_BASE_PHYS+(x))
+#endif
+
+#if 0 /* test-only: also defined in npe/include/... */
+#define IXP425_OSTS	IXP425_TIMER_REG(IXP425_OSTS_OFFSET)
+#endif
+#define IXP425_OST1	IXP425_TIMER_REG(IXP425_OST1_OFFSET)
+#define IXP425_OSRT1	IXP425_TIMER_REG(IXP425_OSRT1_OFFSET)
+#define IXP425_OST2	IXP425_TIMER_REG(IXP425_OST2_OFFSET)
+#define IXP425_OSRT2	IXP425_TIMER_REG(IXP425_OSRT2_OFFSET)
+#define IXP425_OSWT	IXP425_TIMER_REG(IXP425_OSWT_OFFSET)
+#define IXP425_OSWE	IXP425_TIMER_REG(IXP425_OSWE_OFFSET)
+#define IXP425_OSWK	IXP425_TIMER_REG(IXP425_OSWK_OFFSET)
+#define IXP425_OSST	IXP425_TIMER_REG(IXP425_OSST_OFFSET)
+
+/*
+ * Timer register values and bit definitions
+ */
+#define IXP425_OST_ENABLE              BIT(0)
+#define IXP425_OST_ONE_SHOT            BIT(1)
+/* Low order bits of reload value ignored */
+#define IXP425_OST_RELOAD_MASK         (0x3)
+#define IXP425_OST_DISABLED            (0x0)
+#define IXP425_OSST_TIMER_1_PEND       BIT(0)
+#define IXP425_OSST_TIMER_2_PEND       BIT(1)
+#define IXP425_OSST_TIMER_TS_PEND      BIT(2)
+#define IXP425_OSST_TIMER_WDOG_PEND    BIT(3)
+#define IXP425_OSST_TIMER_WARM_RESET   BIT(4)
+
+/*
+ * Constants to make it easy to access PCI Control/Status registers
+ */
+#define PCI_NP_AD_OFFSET            0x00
+#define PCI_NP_CBE_OFFSET           0x04
+#define PCI_NP_WDATA_OFFSET         0x08
+#define PCI_NP_RDATA_OFFSET         0x0c
+#define PCI_CRP_AD_CBE_OFFSET       0x10
+#define PCI_CRP_WDATA_OFFSET        0x14
+#define PCI_CRP_RDATA_OFFSET        0x18
+#define PCI_CSR_OFFSET              0x1c
+#define PCI_ISR_OFFSET              0x20
+#define PCI_INTEN_OFFSET            0x24
+#define PCI_DMACTRL_OFFSET          0x28
+#define PCI_AHBMEMBASE_OFFSET       0x2c
+#define PCI_AHBIOBASE_OFFSET        0x30
+#define PCI_PCIMEMBASE_OFFSET       0x34
+#define PCI_AHBDOORBELL_OFFSET      0x38
+#define PCI_PCIDOORBELL_OFFSET      0x3C
+#define PCI_ATPDMA0_AHBADDR_OFFSET  0x40
+#define PCI_ATPDMA0_PCIADDR_OFFSET  0x44
+#define PCI_ATPDMA0_LENADDR_OFFSET  0x48
+#define PCI_ATPDMA1_AHBADDR_OFFSET  0x4C
+#define PCI_ATPDMA1_PCIADDR_OFFSET  0x50
+#define PCI_ATPDMA1_LENADDR_OFFSET  0x54
+
+/*
+ * PCI Control/Status Registers
+ */
+#define IXP425_PCI_CSR(x) ((volatile u32 *)(IXP425_PCI_CFG_BASE_PHYS+(x)))
+
+#define PCI_NP_AD               IXP425_PCI_CSR(PCI_NP_AD_OFFSET)
+#define PCI_NP_CBE              IXP425_PCI_CSR(PCI_NP_CBE_OFFSET)
+#define PCI_NP_WDATA            IXP425_PCI_CSR(PCI_NP_WDATA_OFFSET)
+#define PCI_NP_RDATA            IXP425_PCI_CSR(PCI_NP_RDATA_OFFSET)
+#define PCI_CRP_AD_CBE          IXP425_PCI_CSR(PCI_CRP_AD_CBE_OFFSET)
+#define PCI_CRP_WDATA           IXP425_PCI_CSR(PCI_CRP_WDATA_OFFSET)
+#define PCI_CRP_RDATA           IXP425_PCI_CSR(PCI_CRP_RDATA_OFFSET)
+#define PCI_CSR                 IXP425_PCI_CSR(PCI_CSR_OFFSET)
+#define PCI_ISR                 IXP425_PCI_CSR(PCI_ISR_OFFSET)
+#define PCI_INTEN               IXP425_PCI_CSR(PCI_INTEN_OFFSET)
+#define PCI_DMACTRL             IXP425_PCI_CSR(PCI_DMACTRL_OFFSET)
+#define PCI_AHBMEMBASE          IXP425_PCI_CSR(PCI_AHBMEMBASE_OFFSET)
+#define PCI_AHBIOBASE           IXP425_PCI_CSR(PCI_AHBIOBASE_OFFSET)
+#define PCI_PCIMEMBASE          IXP425_PCI_CSR(PCI_PCIMEMBASE_OFFSET)
+#define PCI_AHBDOORBELL         IXP425_PCI_CSR(PCI_AHBDOORBELL_OFFSET)
+#define PCI_PCIDOORBELL         IXP425_PCI_CSR(PCI_PCIDOORBELL_OFFSET)
+#define PCI_ATPDMA0_AHBADDR     IXP425_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET)
+#define PCI_ATPDMA0_PCIADDR     IXP425_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET)
+#define PCI_ATPDMA0_LENADDR     IXP425_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET)
+#define PCI_ATPDMA1_AHBADDR     IXP425_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET)
+#define PCI_ATPDMA1_PCIADDR     IXP425_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET)
+#define PCI_ATPDMA1_LENADDR     IXP425_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET)
+
+/*
+ * PCI register values and bit definitions
+ */
+
+/* CSR bit definitions */
+#define PCI_CSR_HOST		BIT(0)
+#define PCI_CSR_ARBEN		BIT(1)
+#define PCI_CSR_ADS		BIT(2)
+#define PCI_CSR_PDS		BIT(3)
+#define PCI_CSR_ABE		BIT(4)
+#define PCI_CSR_DBT		BIT(5)
+#define PCI_CSR_ASE		BIT(8)
+#define PCI_CSR_IC		BIT(15)
+
+/* ISR (Interrupt status) Register bit definitions */
+#define PCI_ISR_PSE		BIT(0)
+#define PCI_ISR_PFE		BIT(1)
+#define PCI_ISR_PPE		BIT(2)
+#define PCI_ISR_AHBE		BIT(3)
+#define PCI_ISR_APDC		BIT(4)
+#define PCI_ISR_PADC		BIT(5)
+#define PCI_ISR_ADB		BIT(6)
+#define PCI_ISR_PDB		BIT(7)
+
+/* INTEN (Interrupt Enable) Register bit definitions */
+#define PCI_INTEN_PSE		BIT(0)
+#define PCI_INTEN_PFE		BIT(1)
+#define PCI_INTEN_PPE		BIT(2)
+#define PCI_INTEN_AHBE		BIT(3)
+#define PCI_INTEN_APDC		BIT(4)
+#define PCI_INTEN_PADC		BIT(5)
+#define PCI_INTEN_ADB		BIT(6)
+#define PCI_INTEN_PDB		BIT(7)
+
+/*
+ * Shift value for byte enable on NP cmd/byte enable register
+ */
+#define IXP425_PCI_NP_CBE_BESL	4
+
+/*
+ * PCI commands supported by NP access unit
+ */
+#define NP_CMD_IOREAD		0x2
+#define NP_CMD_IOWRITE		0x3
+#define NP_CMD_CONFIGREAD	0xa
+#define NP_CMD_CONFIGWRITE	0xb
+#define NP_CMD_MEMREAD		0x6
+#define	NP_CMD_MEMWRITE		0x7
+
+#if 0
+#ifndef __ASSEMBLY__
+extern int ixp425_pci_read(u32 addr, u32 cmd, u32* data);
+extern int ixp425_pci_write(u32 addr, u32 cmd, u32 data);
+extern void ixp425_pci_init(void *);
+#endif
+#endif
+
+/*
+ * Constants for CRP access into local config space
+ */
+#define CRP_AD_CBE_BESL         20
+#define CRP_AD_CBE_WRITE        BIT(16)
+
+/*
+ * Clock Speed Definitions.
+ */
+#define IXP425_PERIPHERAL_BUS_CLOCK (66) /* 66Mhzi APB BUS   */
+
+
+#endif
diff --git a/arch/arm/include/asm/arch-ixp/ixp425pci.h b/arch/arm/include/asm/arch-ixp/ixp425pci.h
new file mode 100644
index 0000000000..9ea3319d84
--- /dev/null
+++ b/arch/arm/include/asm/arch-ixp/ixp425pci.h
@@ -0,0 +1,312 @@
+/*
+ * IXP PCI Init
+ * (C) Copyright 2004 eslab.whut.edu.cn
+ * Yue Hu(huyue_whut@yahoo.com.cn), Ligong Xue(lgxue@hotmail.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _IXP425PCI_H_
+#define _IXP425PCI_H_
+
+#define TRUE	1
+#define FALSE	0
+#define OK	0
+#define ERROR	-1
+#define BOOL	int
+
+#define IXP425_PCI_MAX_BAR_PER_FUNC  6
+#define IXP425_PCI_MAX_BAR (IXP425_PCI_MAX_BAR_PER_FUNC * \
+			    IXP425_PCI_MAX_FUNC_ON_BUS)
+
+enum PciBarId
+{
+	CSR_BAR=0,
+	IO_BAR,
+	SD_BAR,
+	NO_BAR
+};
+
+/*Base address register descriptor*/
+typedef struct
+{
+	unsigned int size;
+	unsigned int address;
+} PciBar;
+
+typedef struct
+{
+	unsigned int bus;
+	unsigned int device;
+	unsigned int func;
+	unsigned int irq;
+	BOOL error;
+	unsigned short vendor_id;
+	unsigned short device_id;
+	/*We need an extra entry in this array for dummy placeholder*/
+	PciBar bar[IXP425_PCI_MAX_BAR_PER_FUNC + 1];
+} PciDevice;
+
+/* Mask definitions*/
+#define IXP425_PCI_TOP_WORD_OF_LONG_MASK	0xffff0000
+#define IXP425_PCI_TOP_BYTE_OF_LONG_MASK	0xff000000
+#define IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK	0x0000ffff
+#define IXP425_PCI_BOTTOM_TRIBYTES_OF_LONG_MASK 0x00ffffff
+#define IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK	0x0000000f
+#define IXP425_PCI_MAX_UINT32			0xffffffff
+
+
+#define IXP425_PCI_BAR_QUERY			0xffffffff
+
+#define IXP425_PCI_BAR_MEM_BASE 0x100000
+#define IXP425_PCI_BAR_IO_BASE	0x000000
+
+/*define the maximum number of bus segments - we support a single segment*/
+#define IXP425_PCI_MAX_BUS  1
+/*define the maximum number of cards per bus segment*/
+#define IXP425_PCI_MAX_DEV  4
+/*define the maximum number of functions per device*/
+#define IXP425_PCI_MAX_FUNC 8
+/* define the maximum number of separate functions that we can
+   potentially have on the bus*/
+#define IXP425_PCI_MAX_FUNC_ON_BUS (1+ IXP425_PCI_MAX_FUNC *	\
+				    IXP425_PCI_MAX_DEV *	\
+				    IXP425_PCI_MAX_BUS)
+/*define the maximum number of BARs per function*/
+#define IXP425_PCI_MAX_BAR_PER_FUNC  6
+#define IXP425_PCI_MAX_BAR (IXP425_PCI_MAX_BAR_PER_FUNC *	\
+			    IXP425_PCI_MAX_FUNC_ON_BUS)
+
+#define PCI_NP_CBE_BESL	 (4)
+#define PCI_NP_AD_FUNCSL (8)
+
+#define REG_WRITE(b,o,v) (*(volatile unsigned int*)((b+o))=(v))
+#define REG_READ(b,o,v)	 ((v)=(*(volatile unsigned int*)((b+o))))
+
+#define PCI_DELAY	500
+#define USEC_LOOP_COUNT 533
+#define PCI_SETTLE_USEC 200
+#define PCI_MIN_RESET_ASSERT_USEC 2000
+
+/*Register addressing definitions for PCI controller configuration
+  and status registers*/
+
+#define PCI_CSR_BASE (0xC0000000)
+/*
+#define PCI_NP_AD_OFFSET       (0x00)
+#define PCI_NP_CBE_OFFSET      (0x04)
+#define PCI_NP_WDATA_OFFSET    (0x08)
+#define PCI_NP_RDATA_OFFSET    (0x0C)
+#define PCI_CRP_OFFSET	       (0x10)
+#define PCI_CRP_WDATA_OFFSET   (0x14)
+#define PCI_CRP_RDATA_OFFSET   (0x18)
+#define PCI_CSR_OFFSET	       (0x1C)
+#define PCI_ISR_OFFSET	       (0x20)
+#define PCI_INTEN_OFFSET       (0x24)
+#define PCI_DMACTRL_OFFSET     (0x28)
+#define PCI_AHBMEMBASE_OFFSET  (0x2C)
+#define PCI_AHBIOBASE_OFFSET   (0x30)
+#define PCI_PCIMEMBASE_OFFSET  (0x34)
+#define PCI_AHBDOORBELL_OFFSET (0x38)
+#define PCI_PCIDOORBELL_OFFSET (0x3C)
+#define PCI_ATPDMA0_AHBADDR    (0x40)
+#define PCI_ATPDMA0_PCIADDR    (0x44)
+#define PCI_ATPDMA0_LENADDR    (0x48)
+#define PCI_ATPDMA1_AHBADDR    (0x4C)
+#define PCI_ATPDMA1_PCIADDR    (0x50)
+#define PCI_ATPDMA1_LENADDR    (0x54)
+#define PCI_PTADMA0_AHBADDR    (0x58)
+#define PCI_PTADMA0_PCIADDR    (0x5C)
+#define PCI_PTADMA0_LENADDR    (0x60)
+#define PCI_PTADMA1_AHBADDR    (0x64)
+#define PCI_PTADMA1_PCIADDR    (0x68)
+#define PCI_PTADMA1_LENADDR    (0x6C)
+*/
+/*Non prefetch registers bit definitions*/
+/*
+#define NP_CMD_INTACK	   (0x0)
+#define NP_CMD_SPECIAL	   (0x1)
+#define NP_CMD_IOREAD	   (0x2)
+#define NP_CMD_IOWRITE	   (0x3)
+#define NP_CMD_MEMREAD	   (0x6)
+#define NP_CMD_MEMWRITE	   (0x7)
+#define NP_CMD_CONFIGREAD  (0xa)
+#define NP_CMD_CONFIGWRITE (0xb)
+*/
+
+/*define the default setting of the AHB memory base reg*/
+#define IXP425_PCI_AHBMEMBASE_DEFAULT 0x00010203
+#define IXP425_PCI_AHBIOBASE_DEFAULT  0x0
+#define IXP425_PCI_PCIMEMBASE_DEFAULT 0x0
+
+/*define the default settings for the controller's BARs*/
+#ifdef IXP425_PCI_SIMPLE_MAPPING
+#define IXP425_PCI_BAR_0_DEFAULT 0x00000000
+#define IXP425_PCI_BAR_1_DEFAULT 0x01000000
+#define IXP425_PCI_BAR_2_DEFAULT 0x02000000
+#define IXP425_PCI_BAR_3_DEFAULT 0x03000000
+#define IXP425_PCI_BAR_4_DEFAULT 0x00000000
+#define IXP425_PCI_BAR_5_DEFAULT 0x00000000
+#else
+#define IXP425_PCI_BAR_0_DEFAULT 0x40000000
+#define IXP425_PCI_BAR_1_DEFAULT 0x41000000
+#define IXP425_PCI_BAR_2_DEFAULT 0x42000000
+#define IXP425_PCI_BAR_3_DEFAULT 0x43000000
+#define IXP425_PCI_BAR_4_DEFAULT 0x00000000
+#define IXP425_PCI_BAR_5_DEFAULT 0x00000000
+#endif
+
+/*Configuration Port register bit definitions*/
+#define PCI_CRP_WRITE BIT(16)
+
+/*ISR (Interrupt status) Register bit definitions*/
+#define PCI_ISR_PSE   BIT(0)
+#define PCI_ISR_PFE   BIT(1)
+#define PCI_ISR_PPE   BIT(2)
+#define PCI_ISR_AHBE  BIT(3)
+#define PCI_ISR_APDC  BIT(4)
+#define PCI_ISR_PADC  BIT(5)
+#define PCI_ISR_ADB   BIT(6)
+#define PCI_ISR_PDB   BIT(7)
+
+/*INTEN (Interrupt Enable) Register bit definitions*/
+#define PCI_INTEN_PSE	BIT(0)
+#define PCI_INTEN_PFE	BIT(1)
+#define PCI_INTEN_PPE	BIT(2)
+#define PCI_INTEN_AHBE	BIT(3)
+#define PCI_INTEN_APDC	BIT(4)
+#define PCI_INTEN_PADC	BIT(5)
+#define PCI_INTEN_ADB	BIT(6)
+#define PCI_INTEN_PDB	BIT(7)
+
+/*PCI configuration regs.*/
+
+#define PCI_CFG_VENDOR_ID	0x00
+#define PCI_CFG_DEVICE_ID	0x02
+#define PCI_CFG_COMMAND		0x04
+#define PCI_CFG_STATUS		0x06
+#define PCI_CFG_REVISION	0x08
+#define PCI_CFG_PROGRAMMING_IF	0x09
+#define PCI_CFG_SUBCLASS	0x0a
+#define PCI_CFG_CLASS		0x0b
+#define PCI_CFG_CACHE_LINE_SIZE 0x0c
+#define PCI_CFG_LATENCY_TIMER	0x0d
+#define PCI_CFG_HEADER_TYPE	0x0e
+#define PCI_CFG_BIST		0x0f
+#define PCI_CFG_BASE_ADDRESS_0	0x10
+#define PCI_CFG_BASE_ADDRESS_1	0x14
+#define PCI_CFG_BASE_ADDRESS_2	0x18
+#define PCI_CFG_BASE_ADDRESS_3	0x1c
+#define PCI_CFG_BASE_ADDRESS_4	0x20
+#define PCI_CFG_BASE_ADDRESS_5	0x24
+#define PCI_CFG_CIS		0x28
+#define PCI_CFG_SUB_VENDOR_ID	0x2c
+#define PCI_CFG_SUB_SYSTEM_ID	0x2e
+#define PCI_CFG_EXPANSION_ROM	0x30
+#define PCI_CFG_RESERVED_0	0x34
+#define PCI_CFG_RESERVED_1	0x38
+#define PCI_CFG_DEV_INT_LINE	0x3c
+#define PCI_CFG_DEV_INT_PIN	0x3d
+#define PCI_CFG_MIN_GRANT	0x3e
+#define PCI_CFG_MAX_LATENCY	0x3f
+#define PCI_CFG_SPECIAL_USE	0x41
+#define PCI_CFG_MODE		0x43
+
+/*Specify the initial command we send to PCI devices*/
+#define INITIAL_PCI_CMD (PCI_CMD_IO_ENABLE	   \
+			 | PCI_CMD_MEM_ENABLE	   \
+			 | PCI_CMD_MASTER_ENABLE   \
+			 | PCI_CMD_WI_ENABLE)
+
+/*define the sub vendor and subsystem to be used */
+#define IXP425_PCI_SUB_VENDOR_SYSTEM 0x00000000
+
+#define PCI_IRQ_LINES		4
+
+#define PCI_CMD_IO_ENABLE	0x0001	/* IO access enable */
+#define PCI_CMD_MEM_ENABLE	0x0002	/* memory access enable */
+#define PCI_CMD_MASTER_ENABLE	0x0004	/* bus master enable */
+#define PCI_CMD_MON_ENABLE	0x0008	/* monitor special cycles enable */
+#define PCI_CMD_WI_ENABLE	0x0010	/* write and invalidate enable */
+#define PCI_CMD_SNOOP_ENABLE	0x0020	/* palette snoop enable */
+#define PCI_CMD_PERR_ENABLE	0x0040	/* parity error enable */
+#define PCI_CMD_WC_ENABLE	0x0080	/* wait cycle enable */
+#define PCI_CMD_SERR_ENABLE	0x0100	/* system error enable */
+#define PCI_CMD_FBTB_ENABLE	0x0200	/* fast back to back enable */
+
+
+/*CSR Register bit definitions*/
+#define PCI_CSR_HOST  BIT(0)
+#define PCI_CSR_ARBEN BIT(1)
+#define PCI_CSR_ADS   BIT(2)
+#define PCI_CSR_PDS   BIT(3)
+#define PCI_CSR_ABE   BIT(4)
+#define PCI_CSR_DBT   BIT(5)
+#define PCI_CSR_ASE   BIT(8)
+#define PCI_CSR_IC    BIT(15)
+
+/*Configuration command bit definitions*/
+#define PCI_CFG_CMD_IOAE BIT(0)
+#define PCI_CFG_CMD_MAE	 BIT(1)
+#define PCI_CFG_CMD_BME	 BIT(2)
+#define PCI_CFG_CMD_MWIE BIT(4)
+#define PCI_CFG_CMD_SER	 BIT(8)
+#define PCI_CFG_CMD_FBBE BIT(9)
+#define PCI_CFG_CMD_MDPE BIT(24)
+#define PCI_CFG_CMD_STA	 BIT(27)
+#define PCI_CFG_CMD_RTA	 BIT(28)
+#define PCI_CFG_CMD_RMA	 BIT(29)
+#define PCI_CFG_CMD_SSE	 BIT(30)
+#define PCI_CFG_CMD_DPE	 BIT(31)
+
+/*DMACTRL DMA Control and status Register*/
+#define PCI_DMACTRL_APDCEN  BIT(0)
+#define PCI_DMACTRL_APDC0   BIT(4)
+#define PCI_DMACTRL_APDE0   BIT(5)
+#define PCI_DMACTRL_APDC1   BIT(6)
+#define PCI_DMACTRL_APDE1   BIT(7)
+#define PCI_DMACTRL_PADCEN  BIT(8)
+#define PCI_DMACTRL_PADC0   BIT(12)
+#define PCI_DMACTRL_PADE0   BIT(13)
+#define PCI_DMACTRL_PADC1   BIT(14)
+#define PCI_DMACTRL_PADE1   BIT(15)
+
+/* GPIO related register */
+#undef IXP425_GPIO_GPOUTR
+#undef IXP425_GPIO_GPOER
+#undef IXP425_GPIO_GPINR
+#undef IXP425_GPIO_GPISR
+#undef IXP425_GPIO_GPIT1R
+#undef IXP425_GPIO_GPIT2R
+#undef IXP425_GPIO_GPCLKR
+
+#define IXP425_GPIO_GPOUTR	0xC8004000
+#define IXP425_GPIO_GPOER	0xC8004004
+#define IXP425_GPIO_GPINR	0xC8004008
+#define IXP425_GPIO_GPISR	0xC800400C
+#define IXP425_GPIO_GPIT1R	0xC8004010
+#define IXP425_GPIO_GPIT2R	0xC8004014
+#define IXP425_GPIO_GPCLKR	0xC8004018
+
+#define READ_GPIO_REG(addr,val) \
+		(val) = *((volatile int *)(addr));
+#define WRITE_GPIO_REG(addr,val) \
+		*((volatile int *)(addr)) = (val);
+
+#endif