diff options
author | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2015-02-24 07:59:38 +0100 |
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committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2015-02-24 07:59:38 +0100 |
commit | e1cc4d31f889428a4ca73120951389c756404184 (patch) | |
tree | 4a2028c750e19f5d36d0aa7545bda7cbacea9dd4 /arch/arm/include/asm/arch-keystone/ddr3.h | |
parent | 23d184d2fbc805bdd9fb41f2370cdce04a7894af (diff) | |
parent | 38dac81b3d0e777f301ca98100bfbcab01d616c2 (diff) |
Merge remote-tracking branch 'u-boot/master' into 'u-boot-arm/master'
Diffstat (limited to 'arch/arm/include/asm/arch-keystone/ddr3.h')
-rw-r--r-- | arch/arm/include/asm/arch-keystone/ddr3.h | 63 |
1 files changed, 0 insertions, 63 deletions
diff --git a/arch/arm/include/asm/arch-keystone/ddr3.h b/arch/arm/include/asm/arch-keystone/ddr3.h deleted file mode 100644 index b044d6f18f..0000000000 --- a/arch/arm/include/asm/arch-keystone/ddr3.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * DDR3 - * - * (C) Copyright 2014 - * Texas Instruments Incorporated, <www.ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _DDR3_H_ -#define _DDR3_H_ - -#include <asm/arch/hardware.h> - -struct ddr3_phy_config { - unsigned int pllcr; - unsigned int pgcr1_mask; - unsigned int pgcr1_val; - unsigned int ptr0; - unsigned int ptr1; - unsigned int ptr2; - unsigned int ptr3; - unsigned int ptr4; - unsigned int dcr_mask; - unsigned int dcr_val; - unsigned int dtpr0; - unsigned int dtpr1; - unsigned int dtpr2; - unsigned int mr0; - unsigned int mr1; - unsigned int mr2; - unsigned int dtcr; - unsigned int pgcr2; - unsigned int zq0cr1; - unsigned int zq1cr1; - unsigned int zq2cr1; - unsigned int pir_v1; - unsigned int pir_v2; -}; - -struct ddr3_emif_config { - unsigned int sdcfg; - unsigned int sdtim1; - unsigned int sdtim2; - unsigned int sdtim3; - unsigned int sdtim4; - unsigned int zqcfg; - unsigned int sdrfc; -}; - -void ddr3_init(void); -int ddr3_get_size(void); -void ddr3_reset_ddrphy(void); -void ddr3_init_ecc(u32 base); -void ddr3_disable_ecc(u32 base); -void ddr3_check_ecc_int(u32 base); -int ddr3_ecc_support_rmw(u32 base); -void ddr3_err_reset_workaround(void); -void ddr3_enable_ecc(u32 base, int test); -void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg); -void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg); - -#endif |