diff options
| author | Wang Huan <b18965@freescale.com> | 2014-09-05 13:52:34 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-09-08 10:30:32 -0700 |
| commit | d60a2099a20254b33a314895a4b5e6a21aebd135 (patch) | |
| tree | 2fb79855edd6466a89c84cc4ce6210802aa75d06 /arch/arm/include/asm/arch-ls102xa/imx-regs.h | |
| parent | d6c1ffc7d23f4fe4ae8c91101861055b8e1501b6 (diff) | |
arm: ls102xa: Add Freescale LS102xA SoC support
The QorIQ LS1 family is built on Layerscape architecture,
the industry's first software-aware, core-agnostic networking
architecture to offer unprecedented efficiency and scale.
Freescale LS102xA is a set of SoCs combines two ARM
Cortex-A7 cores that have been optimized for high
reliability and pack the highest level of integration
available for sub-3 W embedded communications processors
with Layerscape architecture and with a comprehensive
enablement model focused on ease of programmability.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Jason Jin <jason.jin@freescale.com>
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Diffstat (limited to 'arch/arm/include/asm/arch-ls102xa/imx-regs.h')
| -rw-r--r-- | arch/arm/include/asm/arch-ls102xa/imx-regs.h | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-ls102xa/imx-regs.h b/arch/arm/include/asm/arch-ls102xa/imx-regs.h new file mode 100644 index 0000000000..f9cd75b021 --- /dev/null +++ b/arch/arm/include/asm/arch-ls102xa/imx-regs.h @@ -0,0 +1,53 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#ifndef __ASM_ARCH_IMX_REGS_H__ +#define __ASM_ARCH_IMX_REGS_H__ + +#define I2C_QUIRK_REG /* enable 8-bit driver */ + +#ifdef CONFIG_LPUART_32B_REG +struct lpuart_fsl { + u32 baud; + u32 stat; + u32 ctrl; + u32 data; + u32 match; + u32 modir; + u32 fifo; + u32 water; +}; +#else +struct lpuart_fsl { + u8 ubdh; + u8 ubdl; + u8 uc1; + u8 uc2; + u8 us1; + u8 us2; + u8 uc3; + u8 ud; + u8 uma1; + u8 uma2; + u8 uc4; + u8 uc5; + u8 ued; + u8 umodem; + u8 uir; + u8 reserved; + u8 upfifo; + u8 ucfifo; + u8 usfifo; + u8 utwfifo; + u8 utcfifo; + u8 urwfifo; + u8 urcfifo; + u8 rsvd[28]; +}; +#endif + +#endif /* __ASM_ARCH_IMX_REGS_H__ */ |