diff options
| author | Neil Armstrong <narmstrong@baylibre.com> | 2018-07-27 14:10:00 +0200 |
|---|---|---|
| committer | Neil Armstrong <narmstrong@baylibre.com> | 2018-11-26 14:40:52 +0100 |
| commit | d96a782d09dbdc4a28ece3d18dc17a572e39d4f2 (patch) | |
| tree | a703759f1ed5f4bde82bceb9ec377a5e31f20ac7 /arch/arm/include/asm/arch-meson/gx.h | |
| parent | b890acc7432e2ca7b21a44cc70a87aca51b0aedd (diff) | |
ARM: meson: Add boot device discovery
The Amlogic Meson SoCs ROM supports a boot over USB with a custom protocol.
When no other boot medium are available (or by forcing the USB mode), the
ROM sets the primary USB port as device mode and waits for a Host to
enumerate.
When enumerated, a custom protocol described at [1] permits writing to
memory and execute some specific FIP init code to run the loaded
Arm Trusted Firmware BL2 and BL3 stages before running the BL33 stage.
In this mode, we can load different binaries that can be used by U-boot
like a script image file.
This adds support for a custom USB boot stage only available when the
boot mode is USB and the script file at a pre-defined address is valid.
This support was heavily copied from the Sunxi Allwinner FEL U-Boot support.
The tool pyamlboot described at [2], permits using this boot mode on boards
exposing the first USB port, either as OTG or Host port.
[1] https://github.com/superna9999/pyamlboot/blob/master/PROTOCOL.md
[2] https://github.com/superna9999/pyamlboot/blob/master/README.md
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Diffstat (limited to 'arch/arm/include/asm/arch-meson/gx.h')
| -rw-r--r-- | arch/arm/include/asm/arch-meson/gx.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-meson/gx.h b/arch/arm/include/asm/arch-meson/gx.h index 4bc9475d35..b781ba9475 100644 --- a/arch/arm/include/asm/arch-meson/gx.h +++ b/arch/arm/include/asm/arch-meson/gx.h @@ -21,6 +21,7 @@ #define GX_AO_SEC_GP_CFG4 GX_AO_ADDR(0x94) #define GX_AO_SEC_GP_CFG5 GX_AO_ADDR(0x95) +#define GX_AO_BOOT_DEVICE 0xF #define GX_AO_MEM_SIZE_MASK 0xFFFF0000 #define GX_AO_MEM_SIZE_SHIFT 16 #define GX_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000 |