diff options
| author | Peng Fan <Peng.Fan@freescale.com> | 2015-07-01 17:01:50 +0800 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2015-07-10 09:36:16 +0200 |
| commit | 19c6ec70c59da076f0e516841caa7d9c14f501b4 (patch) | |
| tree | 61ad0540e021f602870359a58b6050cf386c8b82 /arch/arm/include/asm/arch-mx6/crm_regs.h | |
| parent | 2d59acc70f76e6d52cc9a226c55539c9353a23cb (diff) | |
imx: mx6 add i2c4 clock support for i.MX6SX
Add I2C4 clock support for i.MX6SX. Since we use runtime check,
but not macro, we need to remove `#ifdef ..` in crm_regs.h, or
gcc will fail to compile the code succesfully.
Making the macros only for i.MX6SX open to other i.MX6x maybe not
a good choice, but we have runtime check.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Diffstat (limited to 'arch/arm/include/asm/arch-mx6/crm_regs.h')
| -rw-r--r-- | arch/arm/include/asm/arch-mx6/crm_regs.h | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 887d04850f..98415ace02 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -740,7 +740,7 @@ struct mxc_ccm_reg { #define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET) #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10 #define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET) -#ifdef CONFIG_MX6SX +/* The following *CCGR6* exist only i.MX6SX */ #define MXC_CCM_CCGR6_PWM8_OFFSET 16 #define MXC_CCM_CCGR6_PWM8_MASK (3 << MXC_CCM_CCGR6_PWM8_OFFSET) #define MXC_CCM_CCGR6_VADC_OFFSET 20 @@ -755,10 +755,9 @@ struct mxc_ccm_reg { #define MXC_CCM_CCGR6_PWM6_MASK (3 << MXC_CCM_CCGR6_PWM6_OFFSET) #define MXC_CCM_CCGR6_PWM7_OFFSET 30 #define MXC_CCM_CCGR6_PWM7_MASK (3 << MXC_CCM_CCGR6_PWM7_OFFSET) -#else +/* The two does not exist on i.MX6SX */ #define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12 #define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET) -#endif #define BM_ANADIG_PLL_SYS_LOCK 0x80000000 #define BP_ANADIG_PLL_SYS_RSVD0 20 |