diff options
| author | Peng Fan <Peng.Fan@freescale.com> | 2015-07-20 19:28:24 +0800 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2015-08-02 11:05:07 +0200 |
| commit | d73d5aee3c5585e67ece5f6e263259fceaadf890 (patch) | |
| tree | e9ad666d4db8e2969fa3e61c71a73a3545ab785a /arch/arm/include/asm/arch-mx6/imx-regs.h | |
| parent | bc32fc699c18c690cfb9c448a0f6dca1f020d277 (diff) | |
imx: mx6ul Add CONFIG_SYS_CACHELINE_SIZE for i.MX6UL
Since i.MX6UL's cache line size is 64bytes, need to
define the macro CONFIG_SYS_CACHELINE_SIZE to 64 for i.MX6UL.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Diffstat (limited to 'arch/arm/include/asm/arch-mx6/imx-regs.h')
| -rw-r--r-- | arch/arm/include/asm/arch-mx6/imx-regs.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index d8b5d6f767..4d84a9b753 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -9,7 +9,11 @@ #define ARCH_MXC +#ifdef CONFIG_MX6UL +#define CONFIG_SYS_CACHELINE_SIZE 64 +#else #define CONFIG_SYS_CACHELINE_SIZE 32 +#endif #define ROMCP_ARB_BASE_ADDR 0x00000000 #define ROMCP_ARB_END_ADDR 0x000FFFFF |