diff options
author | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2015-02-24 07:59:38 +0100 |
---|---|---|
committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2015-02-24 07:59:38 +0100 |
commit | e1cc4d31f889428a4ca73120951389c756404184 (patch) | |
tree | 4a2028c750e19f5d36d0aa7545bda7cbacea9dd4 /arch/arm/include/asm/arch-mx6 | |
parent | 23d184d2fbc805bdd9fb41f2370cdce04a7894af (diff) | |
parent | 38dac81b3d0e777f301ca98100bfbcab01d616c2 (diff) |
Merge remote-tracking branch 'u-boot/master' into 'u-boot-arm/master'
Diffstat (limited to 'arch/arm/include/asm/arch-mx6')
-rw-r--r-- | arch/arm/include/asm/arch-mx6/imx-regs.h | 16 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-mx6/mx6-ddr.h | 46 |
2 files changed, 56 insertions, 6 deletions
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index c968600b77..ae88b6ecab 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -88,8 +88,8 @@ #define AIPS2_ARB_BASE_ADDR 0x02100000 #define AIPS2_ARB_END_ADDR 0x021FFFFF #ifdef CONFIG_MX6SX -#define AIPS3_BASE_ADDR 0x02200000 -#define AIPS3_END_ADDR 0x022FFFFF +#define AIPS3_ARB_BASE_ADDR 0x02200000 +#define AIPS3_ARB_END_ADDR 0x022FFFFF #define WEIM_ARB_BASE_ADDR 0x50000000 #define WEIM_ARB_END_ADDR 0x57FFFFFF #define QSPI0_AMBA_BASE 0x60000000 @@ -624,12 +624,16 @@ struct fuse_bank0_regs { u32 rsvd1[3]; u32 uid_high; u32 rsvd2[3]; - u32 rsvd3[4]; - u32 rsvd4[4]; - u32 rsvd5[4]; + u32 cfg2; + u32 rsvd3[3]; + u32 cfg3; + u32 rsvd4[3]; + u32 cfg4; + u32 rsvd5[3]; u32 cfg5; u32 rsvd6[3]; - u32 rsvd7[4]; + u32 cfg6; + u32 rsvd7[3]; }; #ifdef CONFIG_MX6SX diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h index 5ebabfa271..8e0d7d15c1 100644 --- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h +++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h @@ -62,6 +62,49 @@ struct mmdc_p_regs { u32 mpmur0; }; +#define MX6SX_IOM_DDR_BASE 0x020e0200 +struct mx6sx_iomux_ddr_regs { + u32 res1[59]; + u32 dram_dqm0; + u32 dram_dqm1; + u32 dram_dqm2; + u32 dram_dqm3; + u32 dram_ras; + u32 dram_cas; + u32 res2[2]; + u32 dram_sdwe_b; + u32 dram_odt0; + u32 dram_odt1; + u32 dram_sdba0; + u32 dram_sdba1; + u32 dram_sdba2; + u32 dram_sdcke0; + u32 dram_sdcke1; + u32 dram_sdclk_0; + u32 dram_sdqs0; + u32 dram_sdqs1; + u32 dram_sdqs2; + u32 dram_sdqs3; + u32 dram_reset; +}; + +#define MX6SX_IOM_GRP_BASE 0x020e0500 +struct mx6sx_iomux_grp_regs { + u32 res1[61]; + u32 grp_addds; + u32 grp_ddrmode_ctl; + u32 grp_ddrpke; + u32 grp_ddrpk; + u32 grp_ddrhys; + u32 grp_ddrmode; + u32 grp_b0ds; + u32 grp_b1ds; + u32 grp_ctlds; + u32 grp_ddr_type; + u32 grp_b2ds; + u32 grp_b3ds; +}; + /* * MMDC iomux registers (pinctl/padctl) - (different for IMX6DQ vs IMX6SDL) */ @@ -243,6 +286,9 @@ void mx6dq_dram_iocfg(unsigned width, void mx6sdl_dram_iocfg(unsigned width, const struct mx6sdl_iomux_ddr_regs *, const struct mx6sdl_iomux_grp_regs *); +void mx6sx_dram_iocfg(unsigned width, + const struct mx6sx_iomux_ddr_regs *, + const struct mx6sx_iomux_grp_regs *); /* configure mx6 mmdc registers */ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *, |