diff options
| author | Marek Vasut <marex@denx.de> | 2020-05-30 02:14:48 +0200 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2020-06-08 10:42:54 +0200 |
| commit | 0e06d63d195670f5181958f43216d7106c05357f (patch) | |
| tree | 2f4e9d5515b5db81a3f9a09c64a1e18d81832bda /arch/arm/include/asm/arch-mx7/imx-regs.h | |
| parent | 661d9afe1429e28adcaacd277ab9f28e3790e93f (diff) | |
ARM: imx: ddr: Add missing PHY reset
The iMX7D RM 9.2.4.9.3 Power removal flow Table 9-11. Re-enabling power
explicitly says both the DDR controller and the PHY must be reset in the
correct sequence. Currently the code only resets the controller. This
leads to a misbehavior where the system brings the DRAM up after reboot,
but the DRAM is unstable. Add the missing reset.
The easiest way to trigger this is by triggering WDT without having the
WDT assert WDOG_B signal, i.e. mw.w 0x30280000 0x25 .
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'arch/arm/include/asm/arch-mx7/imx-regs.h')
| -rw-r--r-- | arch/arm/include/asm/arch-mx7/imx-regs.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h index 95238dcaa8..f37419c07f 100644 --- a/arch/arm/include/asm/arch-mx7/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7/imx-regs.h @@ -274,6 +274,7 @@ struct src { #define SRC_DDRC_RCR_DDRC_CORE_RST_OFFSET 1 #define SRC_DDRC_RCR_DDRC_CORE_RST_MASK (1 << 1) +#define SRC_DDRC_RCR_DDRC_PRST_MASK (1 << 0) /* GPR0 Bit Fields */ #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_MASK 0x1u |