diff options
| author | Suman Anna <s-anna@ti.com> | 2016-11-23 12:54:40 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-12-04 13:54:48 -0500 |
| commit | fba82eb7c9eea2fcf5fa05c45cbec26c3410f9f3 (patch) | |
| tree | 2c5ff32c2feba1b0fd5156ce8c266b02054f0b36 /arch/arm/include/asm/arch-omap5 | |
| parent | beb71279d865deb77b2faa86d7d1d180df8339a0 (diff) | |
ARM: DRA7: Redefine voltage and efuse macros per OPP using Kconfig
Redefine the macros used to define the voltage values and the
efuse register offsets based on OPP for all the voltage domains.
This is done using Kconfig macros that can be set in a defconfig
or selected during a config step. This allows a voltage domain
to be configured/set to a corresponding voltage value depending
on the OPP selection choice.
The Kconfig choices have been added for MPU, DSPEVE, IVA and GPU
voltage domains, with the MPU domain restricted to OPP_NOM. The
OPP_OD and OPP_HIGH options will be added when the support for
configuring the MPU clock frequency is added. The clock
configuration for other voltage domains is out of scope in
u-boot code.
The CORE voltage domain does not have separate voltage values
and efuse register offset at different OPPs, while the MPU
voltage domain only has different efuse register offsets for
different OPPs, but uses the same voltage value. Any different
choices of OPPs for voltage domains on common ganged-rails
is automatically taken care to select the corresponding
highest OPP voltage value.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/include/asm/arch-omap5')
| -rw-r--r-- | arch/arm/include/asm/arch-omap5/clock.h | 47 |
1 files changed, 34 insertions, 13 deletions
diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index f6ea1df1a4..57287ff36c 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -286,19 +286,40 @@ /* STD_FUSE_OPP_VMIN_MPU_4 */ #define STD_FUSE_OPP_VMIN_MPU_HIGH (DRA752_EFUSE_BASE + 0x1B28) -/* Common voltage and Efuse register macros */ -/* DRA74x/DRA75x/DRA72x */ -#define VDD_MPU_DRA7 VDD_MPU_DRA7_NOM -#define VDD_CORE_DRA7 VDD_CORE_DRA7_NOM -#define VDD_EVE_DRA7 VDD_EVE_DRA7_NOM -#define VDD_GPU_DRA7 VDD_GPU_DRA7_NOM -#define VDD_IVA_DRA7 VDD_IVA_DRA7_NOM - -#define STD_FUSE_OPP_VMIN_MPU STD_FUSE_OPP_VMIN_MPU_NOM -#define STD_FUSE_OPP_VMIN_CORE STD_FUSE_OPP_VMIN_CORE_NOM -#define STD_FUSE_OPP_VMIN_DSPEVE STD_FUSE_OPP_VMIN_DSPEVE_NOM -#define STD_FUSE_OPP_VMIN_GPU STD_FUSE_OPP_VMIN_GPU_NOM -#define STD_FUSE_OPP_VMIN_IVA STD_FUSE_OPP_VMIN_IVA_NOM +#if defined(CONFIG_DRA7_MPU_OPP_HIGH) +#define DRA7_MPU_OPP OPP_HIGH +#elif defined(CONFIG_DRA7_MPU_OPP_OD) +#define DRA7_MPU_OPP OPP_OD +#else /* OPP_NOM default */ +#define DRA7_MPU_OPP OPP_NOM +#endif + +/* OPP_NOM only available option for CORE */ +#define DRA7_CORE_OPP OPP_NOM + +#if defined(CONFIG_DRA7_DSPEVE_OPP_HIGH) +#define DRA7_DSPEVE_OPP OPP_HIGH +#elif defined(CONFIG_DRA7_DSPEVE_OPP_OD) +#define DRA7_DSPEVE_OPP OPP_OD +#else /* OPP_NOM default */ +#define DRA7_DSPEVE_OPP OPP_NOM +#endif + +#if defined(CONFIG_DRA7_IVA_OPP_HIGH) +#define DRA7_IVA_OPP OPP_HIGH +#elif defined(CONFIG_DRA7_IVA_OPP_OD) +#define DRA7_IVA_OPP OPP_OD +#else /* OPP_NOM default */ +#define DRA7_IVA_OPP OPP_NOM +#endif + +#if defined(CONFIG_DRA7_GPU_OPP_HIGH) +#define DRA7_GPU_OPP OPP_HIGH +#elif defined(CONFIG_DRA7_GPU_OPP_OD) +#define DRA7_GPU_OPP OPP_OD +#else /* OPP_NOM default */ +#define DRA7_GPU_OPP OPP_NOM +#endif /* Standard offset is 0.5v expressed in uv */ #define PALMAS_SMPS_BASE_VOLT_UV 500000 |