diff options
| author | Tom Rini <trini@konsulko.com> | 2018-03-29 08:25:56 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-03-29 08:25:56 -0400 |
| commit | 2476d26fd307edc84e8257dc1bccefb65547f88a (patch) | |
| tree | d3902f654ff75f2555841cf4594ef01dc1d9f0b9 /arch/arm/include/asm/arch-rockchip/grf_rk3399.h | |
| parent | 81cf7c8d45935a295991fe2cd1df286f0f47511f (diff) | |
| parent | 6837c58666165b7b040bf5a5b9dfebc8354f5883 (diff) | |
Merge git://git.denx.de/u-boot-rockchip
Diffstat (limited to 'arch/arm/include/asm/arch-rockchip/grf_rk3399.h')
| -rw-r--r-- | arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 34 |
1 files changed, 32 insertions, 2 deletions
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h index b541e2caa1..91e8d2d216 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h @@ -324,13 +324,29 @@ struct rk3399_pmusgrf_regs { check_member(rk3399_pmusgrf_regs, slv_secure_con4, 0xe3d4); enum { + /* GRF_GPIO2A_IOMUX */ + GRF_GPIO2A0_SEL_SHIFT = 0, + GRF_GPIO2A0_SEL_MASK = 3 << GRF_GPIO2A0_SEL_SHIFT, + GRF_I2C2_SDA = 2, + GRF_GPIO2A1_SEL_SHIFT = 2, + GRF_GPIO2A1_SEL_MASK = 3 << GRF_GPIO2A1_SEL_SHIFT, + GRF_I2C2_SCL = 2, + GRF_GPIO2A7_SEL_SHIFT = 14, + GRF_GPIO2A7_SEL_MASK = 3 << GRF_GPIO2A7_SEL_SHIFT, + GRF_I2C7_SDA = 2, + /* GRF_GPIO2B_IOMUX */ - GRF_GPIO2B1_SEL_SHIFT = 0, + GRF_GPIO2B0_SEL_SHIFT = 0, + GRF_GPIO2B0_SEL_MASK = 3 << GRF_GPIO2B0_SEL_SHIFT, + GRF_I2C7_SCL = 2, + GRF_GPIO2B1_SEL_SHIFT = 2, GRF_GPIO2B1_SEL_MASK = 3 << GRF_GPIO2B1_SEL_SHIFT, GRF_SPI2TPM_RXD = 1, - GRF_GPIO2B2_SEL_SHIFT = 2, + GRF_I2C6_SDA = 2, + GRF_GPIO2B2_SEL_SHIFT = 4, GRF_GPIO2B2_SEL_MASK = 3 << GRF_GPIO2B2_SEL_SHIFT, GRF_SPI2TPM_TXD = 1, + GRF_I2C6_SCL = 2, GRF_GPIO2B3_SEL_SHIFT = 6, GRF_GPIO2B3_SEL_MASK = 3 << GRF_GPIO2B3_SEL_SHIFT, GRF_SPI2TPM_CLK = 1, @@ -414,6 +430,14 @@ enum { GRF_GPIO3C1_SEL_MASK = 3 << GRF_GPIO3C1_SEL_SHIFT, GRF_MAC_TXCLK = 1, + /* GRF_GPIO4A_IOMUX */ + GRF_GPIO4A1_SEL_SHIFT = 2, + GRF_GPIO4A1_SEL_MASK = 3 << GRF_GPIO4A1_SEL_SHIFT, + GRF_I2C1_SDA = 1, + GRF_GPIO4A2_SEL_SHIFT = 4, + GRF_GPIO4A2_SEL_MASK = 3 << GRF_GPIO4A2_SEL_SHIFT, + GRF_I2C1_SCL = 1, + /* GRF_GPIO4B_IOMUX */ GRF_GPIO4B0_SEL_SHIFT = 0, GRF_GPIO4B0_SEL_MASK = 3 << GRF_GPIO4B0_SEL_SHIFT, @@ -575,6 +599,12 @@ enum { PMUGRF_GPIO1B2_SEL_SHIFT = 4, PMUGRF_GPIO1B2_SEL_MASK = 3 << PMUGRF_GPIO1B2_SEL_SHIFT, PMUGRF_SPI1EC_CSN0 = 2, + PMUGRF_GPIO1B3_SEL_SHIFT = 6, + PMUGRF_GPIO1B3_SEL_MASK = 3 << PMUGRF_GPIO1B3_SEL_SHIFT, + PMUGRF_I2C4_SDA = 1, + PMUGRF_GPIO1B4_SEL_SHIFT = 8, + PMUGRF_GPIO1B4_SEL_MASK = 3 << PMUGRF_GPIO1B4_SEL_SHIFT, + PMUGRF_I2C4_SCL = 1, PMUGRF_GPIO1B6_SEL_SHIFT = 12, PMUGRF_GPIO1B6_SEL_MASK = 3 << PMUGRF_GPIO1B6_SEL_SHIFT, PMUGRF_PWM_3B = 1, |