Merge git://git.denx.de/u-boot-rockchip

Here is additional rk3368 and rk3399 support, rv1108 support,
refactoring HDMI video (brought in from Anatolij's tree to resolve
conflicts), some mkimage fixes and a few other things.

11 files changed, 1418 insertions, 106 deletions

diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3036.h b/arch/arm/include/asm/arch-rockchip/cru_rk3036.h
index aaef4b9d73..22278e11ac 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3036.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3036.h
@@ -16,9 +16,9 @@
 #define CORE_PERI_HZ	150000000
 #define CORE_ACLK_HZ	300000000
 
-#define CPU_ACLK_HZ	150000000
-#define CPU_HCLK_HZ	300000000
-#define CPU_PCLK_HZ	300000000
+#define BUS_ACLK_HZ	148500000
+#define BUS_HCLK_HZ	148500000
+#define BUS_PCLK_HZ	74250000
 
 #define PERI_ACLK_HZ	148500000
 #define PERI_HCLK_HZ	148500000
@@ -68,102 +68,102 @@ struct pll_div {
 
 enum {
 	/* PLLCON0*/
-	PLL_POSTDIV1_MASK	= 7,
 	PLL_POSTDIV1_SHIFT	= 12,
-	PLL_FBDIV_MASK		= 0xfff,
+	PLL_POSTDIV1_MASK	= 7 << PLL_POSTDIV1_SHIFT,
 	PLL_FBDIV_SHIFT		= 0,
+	PLL_FBDIV_MASK		= 0xfff,
 
 	/* PLLCON1 */
-	PLL_DSMPD_MASK		= 1,
+	PLL_RST_SHIFT		= 14,
 	PLL_DSMPD_SHIFT		= 12,
-	PLL_LOCK_STATUS_MASK	= 1,
+	PLL_DSMPD_MASK		= 1 << PLL_DSMPD_SHIFT,
 	PLL_LOCK_STATUS_SHIFT	= 10,
-	PLL_POSTDIV2_MASK	= 7,
+	PLL_LOCK_STATUS_MASK	= 1 << PLL_LOCK_STATUS_SHIFT,
 	PLL_POSTDIV2_SHIFT	= 6,
-	PLL_REFDIV_MASK		= 0x3f,
+	PLL_POSTDIV2_MASK	= 7 << PLL_POSTDIV2_SHIFT,
 	PLL_REFDIV_SHIFT	= 0,
-	PLL_RST_SHIFT		= 14,
+	PLL_REFDIV_MASK		= 0x3f,
 
 	/* CRU_MODE */
-	GPLL_MODE_MASK		= 3,
 	GPLL_MODE_SHIFT		= 12,
+	GPLL_MODE_MASK		= 3 << GPLL_MODE_SHIFT,
 	GPLL_MODE_SLOW		= 0,
 	GPLL_MODE_NORM,
 	GPLL_MODE_DEEP,
-	DPLL_MODE_MASK		= 1,
 	DPLL_MODE_SHIFT		= 4,
+	DPLL_MODE_MASK		= 1 << DPLL_MODE_SHIFT,
 	DPLL_MODE_SLOW		= 0,
 	DPLL_MODE_NORM,
-	APLL_MODE_MASK		= 1,
 	APLL_MODE_SHIFT		= 0,
+	APLL_MODE_MASK		= 1 << APLL_MODE_SHIFT,
 	APLL_MODE_SLOW		= 0,
 	APLL_MODE_NORM,
 
 	/* CRU_CLK_SEL0_CON */
-	CPU_CLK_PLL_SEL_MASK	= 3,
-	CPU_CLK_PLL_SEL_SHIFT	= 14,
-	CPU_CLK_PLL_SEL_APLL	= 0,
-	CPU_CLK_PLL_SEL_DPLL,
-	CPU_CLK_PLL_SEL_GPLL,
-	ACLK_CPU_DIV_MASK	= 0x1f,
-	ACLK_CPU_DIV_SHIFT	= 8,
-	CORE_CLK_PLL_SEL_MASK	= 1,
+	BUS_ACLK_PLL_SEL_SHIFT	= 14,
+	BUS_ACLK_PLL_SEL_MASK	= 3 << BUS_ACLK_PLL_SEL_SHIFT,
+	BUS_ACLK_PLL_SEL_APLL	= 0,
+	BUS_ACLK_PLL_SEL_DPLL,
+	BUS_ACLK_PLL_SEL_GPLL,
+	BUS_ACLK_DIV_SHIFT	= 8,
+	BUS_ACLK_DIV_MASK	= 0x1f << BUS_ACLK_DIV_SHIFT,
 	CORE_CLK_PLL_SEL_SHIFT	= 7,
+	CORE_CLK_PLL_SEL_MASK	= 1 << CORE_CLK_PLL_SEL_SHIFT,
 	CORE_CLK_PLL_SEL_APLL	= 0,
 	CORE_CLK_PLL_SEL_GPLL,
-	CORE_DIV_CON_MASK	= 0x1f,
 	CORE_DIV_CON_SHIFT	= 0,
+	CORE_DIV_CON_MASK	= 0x1f << CORE_DIV_CON_SHIFT,
 
 	/* CRU_CLK_SEL1_CON */
-	CPU_PCLK_DIV_MASK	= 7,
-	CPU_PCLK_DIV_SHIFT	= 12,
-	CPU_HCLK_DIV_MASK	= 3,
-	CPU_HCLK_DIV_SHIFT	= 8,
-	CORE_ACLK_DIV_MASK	= 7,
+	BUS_PCLK_DIV_SHIFT	= 12,
+	BUS_PCLK_DIV_MASK	= 7 << BUS_PCLK_DIV_SHIFT,
+	BUS_HCLK_DIV_SHIFT	= 8,
+	BUS_HCLK_DIV_MASK	= 3 << BUS_HCLK_DIV_SHIFT,
 	CORE_ACLK_DIV_SHIFT	= 4,
-	CORE_PERI_DIV_MASK	= 0xf,
+	CORE_ACLK_DIV_MASK	= 7 << CORE_ACLK_DIV_SHIFT,
 	CORE_PERI_DIV_SHIFT	= 0,
+	CORE_PERI_DIV_MASK	= 0xf << CORE_PERI_DIV_SHIFT,
 
 	/* CRU_CLKSEL10_CON */
-	PERI_PLL_SEL_MASK	= 3,
 	PERI_PLL_SEL_SHIFT	= 14,
+	PERI_PLL_SEL_MASK	= 3 << PERI_PLL_SEL_SHIFT,
 	PERI_PLL_APLL		= 0,
 	PERI_PLL_DPLL,
 	PERI_PLL_GPLL,
-	PERI_PCLK_DIV_MASK	= 3,
 	PERI_PCLK_DIV_SHIFT	= 12,
-	PERI_HCLK_DIV_MASK	= 3,
+	PERI_PCLK_DIV_MASK	= 3 << PERI_PCLK_DIV_SHIFT,
 	PERI_HCLK_DIV_SHIFT	= 8,
-	PERI_ACLK_DIV_MASK	= 0x1f,
+	PERI_HCLK_DIV_MASK	= 3 << PERI_HCLK_DIV_SHIFT,
 	PERI_ACLK_DIV_SHIFT	= 0,
+	PERI_ACLK_DIV_MASK	= 0x1f << PERI_ACLK_DIV_SHIFT,
 
 	/* CRU_CLKSEL11_CON */
-	SDIO_DIV_MASK		= 0x7f,
 	SDIO_DIV_SHIFT		= 8,
-	MMC0_DIV_MASK		= 0x7f,
+	SDIO_DIV_MASK		= 0x7f << SDIO_DIV_SHIFT,
 	MMC0_DIV_SHIFT		= 0,
+	MMC0_DIV_MASK		= 0x7f << MMC0_DIV_SHIFT,
 
 	/* CRU_CLKSEL12_CON */
-	EMMC_PLL_MASK		= 3,
 	EMMC_PLL_SHIFT		= 12,
+	EMMC_PLL_MASK		= 3 << EMMC_PLL_SHIFT,
 	EMMC_SEL_APLL		= 0,
 	EMMC_SEL_DPLL,
 	EMMC_SEL_GPLL,
 	EMMC_SEL_24M,
-	SDIO_PLL_MASK		= 3,
 	SDIO_PLL_SHIFT		= 10,
+	SDIO_PLL_MASK		= 3 << SDIO_PLL_SHIFT,
 	SDIO_SEL_APLL		= 0,
 	SDIO_SEL_DPLL,
 	SDIO_SEL_GPLL,
 	SDIO_SEL_24M,
-	MMC0_PLL_MASK		= 3,
 	MMC0_PLL_SHIFT		= 8,
+	MMC0_PLL_MASK		= 3 << MMC0_PLL_SHIFT,
 	MMC0_SEL_APLL		= 0,
 	MMC0_SEL_DPLL,
 	MMC0_SEL_GPLL,
 	MMC0_SEL_24M,
-	EMMC_DIV_MASK		= 0x7f,
 	EMMC_DIV_SHIFT		= 0,
+	EMMC_DIV_MASK		= 0x7f << EMMC_DIV_SHIFT,
 
 	/* CRU_SOFTRST5_CON */
 	DDRCTRL_PSRST_SHIFT	= 11,
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
new file mode 100644
index 0000000000..4910ee7387
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
@@ -0,0 +1,124 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ * Author: Andy Yan <andy.yan@rock-chips.com>
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+#ifndef _ASM_ARCH_CRU_RK3368_H
+#define _ASM_ARCH_CRU_RK3368_H
+
+#include <common.h>
+
+
+/* RK3368 clock numbers */
+enum rk3368_pll_id {
+	APLLB,
+	APLLL,
+	DPLL,
+	CPLL,
+	GPLL,
+	NPLL,
+	PLL_COUNT,
+};
+
+struct rk3368_cru {
+	struct rk3368_pll {
+		unsigned int con0;
+		unsigned int con1;
+		unsigned int con2;
+		unsigned int con3;
+	} pll[6];
+	unsigned int reserved[0x28];
+	unsigned int clksel_con[56];
+	unsigned int reserved1[8];
+	unsigned int clkgate_con[25];
+	unsigned int reserved2[7];
+	unsigned int glb_srst_fst_val;
+	unsigned int glb_srst_snd_val;
+	unsigned int reserved3[0x1e];
+	unsigned int softrst_con[15];
+	unsigned int reserved4[0x11];
+	unsigned int misc_con;
+	unsigned int glb_cnt_th;
+	unsigned int glb_rst_con;
+	unsigned int glb_rst_st;
+	unsigned int reserved5[0x1c];
+	unsigned int sdmmc_con[2];
+	unsigned int sdio0_con[2];
+	unsigned int sdio1_con[2];
+	unsigned int emmc_con[2];
+};
+check_member(rk3368_cru, emmc_con[1], 0x41c);
+
+struct rk3368_clk_priv {
+	struct rk3368_cru *cru;
+	ulong rate;
+	bool has_bwadj;
+};
+
+enum {
+	/* PLL CON0 */
+	PLL_NR_SHIFT			= 8,
+	PLL_NR_MASK			= GENMASK(13, 8),
+	PLL_OD_SHIFT			= 0,
+	PLL_OD_MASK			= GENMASK(3, 0),
+
+	/* PLL CON1 */
+	PLL_LOCK_STA			= BIT(31),
+	PLL_NF_SHIFT			= 0,
+	PLL_NF_MASK			= GENMASK(12, 0),
+
+	/* PLL CON2 */
+	PLL_BWADJ_SHIFT			= 0,
+	PLL_BWADJ_MASK			= GENMASK(11, 0),
+
+	/* PLL CON3 */
+	PLL_MODE_SHIFT			= 8,
+	PLL_MODE_MASK			= GENMASK(9, 8),
+	PLL_MODE_SLOW			= 0,
+	PLL_MODE_NORMAL			= 1,
+	PLL_MODE_DEEP_SLOW		= 3,
+	PLL_RESET_SHIFT			= 5,
+	PLL_RESET			= 1,
+	PLL_RESET_MASK			= GENMASK(5, 5),
+
+	/* CLKSEL12_CON */
+	MCU_STCLK_DIV_SHIFT		= 8,
+	MCU_STCLK_DIV_MASK		= GENMASK(10, 8),
+	MCU_PLL_SEL_SHIFT		= 7,
+	MCU_PLL_SEL_MASK		= BIT(7),
+	MCU_PLL_SEL_CPLL		= 0,
+	MCU_PLL_SEL_GPLL		= 1,
+	MCU_CLK_DIV_SHIFT		= 0,
+	MCU_CLK_DIV_MASK		= GENMASK(4, 0),
+
+	/* CLKSEL51_CON */
+	MMC_PLL_SEL_SHIFT		= 8,
+	MMC_PLL_SEL_MASK		= GENMASK(9, 8),
+	MMC_PLL_SEL_CPLL		= 0,
+	MMC_PLL_SEL_GPLL,
+	MMC_PLL_SEL_USBPHY_480M,
+	MMC_PLL_SEL_24M,
+	MMC_CLK_DIV_SHIFT		= 0,
+	MMC_CLK_DIV_MASK		= GENMASK(6, 0),
+
+	/* SOFTRST1_CON */
+	MCU_PO_SRST_MASK		= BIT(13),
+	MCU_SYS_SRST_MASK		= BIT(12),
+
+	/* GLB_RST_CON */
+	PMU_GLB_SRST_CTRL_SHIFT		= 2,
+	PMU_GLB_SRST_CTRL_MASK		= GENMASK(3, 2),
+	PMU_RST_BY_FST_GLB_SRST 	= 0,
+	PMU_RST_BY_SND_GLB_SRST 	= 1,
+	PMU_RST_DISABLE			= 2,
+	WDT_GLB_SRST_CTRL_SHIFT		= 1,
+	WDT_GLB_SRST_CTRL_MASK		= BIT(1),
+	WDT_TRIGGER_SND_GLB_SRST 	= 0,
+	WDT_TRIGGER_FST_GLB_SRST 	= 1,
+	TSADC_GLB_SRST_CTRL_SHIFT 	= 0,
+	TSADC_GLB_SRST_CTRL_MASK  	= BIT(0),
+	TSADC_TRIGGER_SND_GLB_SRST 	= 0,
+	TSADC_TRIGGER_FST_GLB_SRST 	= 1,
+
+};
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rv1108.h b/arch/arm/include/asm/arch-rockchip/cru_rv1108.h
new file mode 100644
index 0000000000..2a1ae692be
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rv1108.h
@@ -0,0 +1,111 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * Author: Andy Yan <andy.yan@rock-chips.com>
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+#ifndef _ASM_ARCH_CRU_RV1108_H
+#define _ASM_ARCH_CRU_RV1108_H
+
+#include <common.h>
+
+#define OSC_HZ		(24 * 1000 * 1000)
+
+#define APLL_HZ		(600 * 1000000)
+#define GPLL_HZ		(594 * 1000000)
+
+struct rv1108_clk_priv {
+	struct rv1108_cru *cru;
+	ulong rate;
+};
+
+struct rv1108_cru {
+	struct rv1108_pll {
+		unsigned int con0;
+		unsigned int con1;
+		unsigned int con2;
+		unsigned int con3;
+		unsigned int con4;
+		unsigned int con5;
+		unsigned int reserved[2];
+	} pll[3];
+	unsigned int clksel_con[46];
+	unsigned int reserved1[2];
+	unsigned int clkgate_con[20];
+	unsigned int reserved2[4];
+	unsigned int softrst_con[13];
+	unsigned int reserved3[3];
+	unsigned int glb_srst_fst_val;
+	unsigned int glb_srst_snd_val;
+	unsigned int glb_cnt_th;
+	unsigned int misc_con;
+	unsigned int glb_rst_con;
+	unsigned int glb_rst_st;
+	unsigned int sdmmc_con[2];
+	unsigned int sdio_con[2];
+	unsigned int emmc_con[2];
+};
+check_member(rv1108_cru, emmc_con[1], 0x01ec);
+
+struct pll_div {
+	u32 refdiv;
+	u32 fbdiv;
+	u32 postdiv1;
+	u32 postdiv2;
+	u32 frac;
+};
+
+enum {
+	/* PLL CON0 */
+	FBDIV_MASK		= 0xfff,
+	FBDIV_SHIFT		= 0,
+
+	/* PLL CON1 */
+	POSTDIV2_SHIFT          = 12,
+	POSTDIV2_MASK		= 7 << POSTDIV2_SHIFT,
+	POSTDIV1_SHIFT          = 8,
+	POSTDIV1_MASK		= 7 << POSTDIV1_SHIFT,
+	REFDIV_MASK		= 0x3f,
+	REFDIV_SHIFT		= 0,
+
+	/* PLL CON2 */
+	LOCK_STA_SHIFT          = 31,
+	LOCK_STA_MASK		= 1 << LOCK_STA_SHIFT,
+	FRACDIV_MASK		= 0xffffff,
+	FRACDIV_SHIFT		= 0,
+
+	/* PLL CON3 */
+	WORK_MODE_SHIFT         = 8,
+	WORK_MODE_MASK		= 1 << WORK_MODE_SHIFT,
+	WORK_MODE_SLOW		= 0,
+	WORK_MODE_NORMAL	= 1,
+	DSMPD_SHIFT             = 3,
+	DSMPD_MASK		= 1 << DSMPD_SHIFT,
+
+	/* CLKSEL0_CON */
+	CORE_PLL_SEL_SHIFT	= 8,
+	CORE_PLL_SEL_MASK	= 3 << CORE_PLL_SEL_SHIFT,
+	CORE_PLL_SEL_APLL	= 0,
+	CORE_PLL_SEL_GPLL	= 1,
+	CORE_PLL_SEL_DPLL	= 2,
+	CORE_CLK_DIV_SHIFT	= 0,
+	CORE_CLK_DIV_MASK	= 0x1f << CORE_CLK_DIV_SHIFT,
+
+	/* CLKSEL24_CON */
+	MAC_PLL_SEL_SHIFT	= 12,
+	MAC_PLL_SEL_MASK	= 1 << MAC_PLL_SEL_SHIFT,
+	MAC_PLL_SEL_APLL	= 0,
+	MAC_PLL_SEL_GPLL	= 1,
+	RMII_EXTCLK_SEL_SHIFT   = 8,
+	RMII_EXTCLK_SEL_MASK	= 1 << RMII_EXTCLK_SEL_SHIFT,
+	MAC_CLK_DIV_MASK	= 0x1f,
+	MAC_CLK_DIV_SHIFT	= 0,
+
+	/* CLKSEL27_CON */
+	SFC_PLL_SEL_SHIFT	= 7,
+	SFC_PLL_SEL_MASK	= 1 << SFC_PLL_SEL_SHIFT,
+	SFC_PLL_SEL_DPLL	= 0,
+	SFC_PLL_SEL_GPLL	= 1,
+	SFC_CLK_DIV_SHIFT	= 0,
+	SFC_CLK_DIV_MASK	= 0x3f << SFC_CLK_DIV_SHIFT,
+};
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3036.h b/arch/arm/include/asm/arch-rockchip/grf_rk3036.h
index 72d133c1a9..7625f249bd 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3036.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3036.h
@@ -83,57 +83,56 @@ check_member(rk3036_grf, sdmmc_det_cnt, 0x304);
 /* GRF_GPIO0A_IOMUX */
 enum {
 	GPIO0A3_SHIFT		= 6,
-	GPIO0A3_MASK		= 1,
+	GPIO0A3_MASK		= 1 << GPIO0A3_SHIFT,
 	GPIO0A3_GPIO		= 0,
 	GPIO0A3_I2C1_SDA,
 
 	GPIO0A2_SHIFT		= 4,
-	GPIO0A2_MASK		= 1,
+	GPIO0A2_MASK		= 1 << GPIO0A2_SHIFT,
 	GPIO0A2_GPIO		= 0,
 	GPIO0A2_I2C1_SCL,
 
 	GPIO0A1_SHIFT		= 2,
-	GPIO0A1_MASK		= 3,
+	GPIO0A1_MASK		= 3 << GPIO0A1_SHIFT,
 	GPIO0A1_GPIO		= 0,
 	GPIO0A1_I2C0_SDA,
 	GPIO0A1_PWM2,
 
 	GPIO0A0_SHIFT		= 0,
-	GPIO0A0_MASK		= 3,
+	GPIO0A0_MASK		= 3 << GPIO0A0_SHIFT,
 	GPIO0A0_GPIO		= 0,
 	GPIO0A0_I2C0_SCL,
 	GPIO0A0_PWM1,
-
 };
 
 /* GRF_GPIO0B_IOMUX */
 enum {
 	GPIO0B6_SHIFT		= 12,
-	GPIO0B6_MASK		= 3,
+	GPIO0B6_MASK		= 3 << GPIO0B6_SHIFT,
 	GPIO0B6_GPIO		= 0,
 	GPIO0B6_MMC1_D3,
 	GPIO0B6_I2S1_SCLK,
 
 	GPIO0B5_SHIFT		= 10,
-	GPIO0B5_MASK		= 3,
+	GPIO0B5_MASK		= 3 << GPIO0B5_SHIFT,
 	GPIO0B5_GPIO		= 0,
 	GPIO0B5_MMC1_D2,
 	GPIO0B5_I2S1_SDI,
 
 	GPIO0B4_SHIFT		= 8,
-	GPIO0B4_MASK		= 3,
+	GPIO0B4_MASK		= 3 << GPIO0B4_SHIFT,
 	GPIO0B4_GPIO		= 0,
 	GPIO0B4_MMC1_D1,
 	GPIO0B4_I2S1_LRCKTX,
 
 	GPIO0B3_SHIFT		= 6,
-	GPIO0B3_MASK		= 3,
+	GPIO0B3_MASK		= 3 << GPIO0B3_SHIFT,
 	GPIO0B3_GPIO		= 0,
 	GPIO0B3_MMC1_D0,
 	GPIO0B3_I2S1_LRCKRX,
 
 	GPIO0B1_SHIFT		= 2,
-	GPIO0B1_MASK		= 3,
+	GPIO0B1_MASK		= 3 << GPIO0B1_SHIFT,
 	GPIO0B1_GPIO		= 0,
 	GPIO0B1_MMC1_CLKOUT,
 	GPIO0B1_I2S1_MCLK,
@@ -148,28 +147,28 @@ enum {
 /* GRF_GPIO0C_IOMUX */
 enum {
 	GPIO0C4_SHIFT		= 8,
-	GPIO0C4_MASK		= 1,
+	GPIO0C4_MASK		= 1 << GPIO0C4_SHIFT,
 	GPIO0C4_GPIO		= 0,
 	GPIO0C4_DRIVE_VBUS,
 
 	GPIO0C3_SHIFT		= 6,
-	GPIO0C3_MASK		= 1,
+	GPIO0C3_MASK		= 1 << GPIO0C3_SHIFT,
 	GPIO0C3_GPIO		= 0,
 	GPIO0C3_UART0_CTSN,
 
 	GPIO0C2_SHIFT		= 4,
-	GPIO0C2_MASK		= 1,
+	GPIO0C2_MASK		= 1 << GPIO0C2_SHIFT,
 	GPIO0C2_GPIO		= 0,
 	GPIO0C2_UART0_RTSN,
 
 	GPIO0C1_SHIFT		= 2,
-	GPIO0C1_MASK		= 1,
+	GPIO0C1_MASK		= 1 << GPIO0C1_SHIFT,
 	GPIO0C1_GPIO		= 0,
 	GPIO0C1_UART0_SIN,
 
 
 	GPIO0C0_SHIFT		= 0,
-	GPIO0C0_MASK		= 1,
+	GPIO0C0_MASK		= 1 << GPIO0C0_SHIFT,
 	GPIO0C0_GPIO		= 0,
 	GPIO0C0_UART0_SOUT,
 };
@@ -177,17 +176,17 @@ enum {
 /* GRF_GPIO0D_IOMUX */
 enum {
 	GPIO0D4_SHIFT		= 8,
-	GPIO0D4_MASK		= 1,
+	GPIO0D4_MASK		= 1 << GPIO0D4_SHIFT,
 	GPIO0D4_GPIO		= 0,
 	GPIO0D4_SPDIF,
 
 	GPIO0D3_SHIFT		= 6,
-	GPIO0D3_MASK		= 1,
+	GPIO0D3_MASK		= 1 << GPIO0D3_SHIFT,
 	GPIO0D3_GPIO		= 0,
 	GPIO0D3_PWM3,
 
 	GPIO0D2_SHIFT		= 4,
-	GPIO0D2_MASK		= 1,
+	GPIO0D2_MASK		= 1 << GPIO0D2_SHIFT,
 	GPIO0D2_GPIO		= 0,
 	GPIO0D2_PWM0,
 };
@@ -195,33 +194,33 @@ enum {
 /* GRF_GPIO1A_IOMUX */
 enum {
 	GPIO1A5_SHIFT		= 10,
-	GPIO1A5_MASK		= 1,
+	GPIO1A5_MASK		= 1 << GPIO1A5_SHIFT,
 	GPIO1A5_GPIO		= 0,
 	GPIO1A5_I2S_SDI,
 
 	GPIO1A4_SHIFT		= 8,
-	GPIO1A4_MASK		= 1,
+	GPIO1A4_MASK		= 1 << GPIO1A4_SHIFT,
 	GPIO1A4_GPIO		= 0,
 	GPIO1A4_I2S_SD0,
 
 	GPIO1A3_SHIFT		= 6,
-	GPIO1A3_MASK		= 1,
+	GPIO1A3_MASK		= 1 << GPIO1A3_SHIFT,
 	GPIO1A3_GPIO		= 0,
 	GPIO1A3_I2S_LRCKTX,
 
 	GPIO1A2_SHIFT		= 4,
-	GPIO1A2_MASK		= 6,
+	GPIO1A2_MASK		= 6 << GPIO1A2_SHIFT,
 	GPIO1A2_GPIO		= 0,
 	GPIO1A2_I2S_LRCKRX,
 	GPIO1A2_I2S_PWM1_0,
 
 	GPIO1A1_SHIFT		= 2,
-	GPIO1A1_MASK		= 1,
+	GPIO1A1_MASK		= 1 << GPIO1A1_SHIFT,
 	GPIO1A1_GPIO		= 0,
 	GPIO1A1_I2S_SCLK,
 
 	GPIO1A0_SHIFT		= 0,
-	GPIO1A0_MASK		= 1,
+	GPIO1A0_MASK		= 1 << GPIO1A0_SHIFT,
 	GPIO1A0_GPIO		= 0,
 	GPIO1A0_I2S_MCLK,
 
@@ -230,27 +229,27 @@ enum {
 /* GRF_GPIO1B_IOMUX */
 enum {
 	GPIO1B7_SHIFT		= 14,
-	GPIO1B7_MASK		= 1,
+	GPIO1B7_MASK		= 1 << GPIO1B7_SHIFT,
 	GPIO1B7_GPIO		= 0,
 	GPIO1B7_MMC0_CMD,
 
 	GPIO1B3_SHIFT		= 6,
-	GPIO1B3_MASK		= 1,
+	GPIO1B3_MASK		= 1 << GPIO1B3_SHIFT,
 	GPIO1B3_GPIO		= 0,
 	GPIO1B3_HDMI_HPD,
 
 	GPIO1B2_SHIFT		= 4,
-	GPIO1B2_MASK		= 1,
+	GPIO1B2_MASK		= 1 << GPIO1B2_SHIFT,
 	GPIO1B2_GPIO		= 0,
 	GPIO1B2_HDMI_SCL,
 
 	GPIO1B1_SHIFT		= 2,
-	GPIO1B1_MASK		= 1,
+	GPIO1B1_MASK		= 1 << GPIO1B1_SHIFT,
 	GPIO1B1_GPIO		= 0,
 	GPIO1B1_HDMI_SDA,
 
 	GPIO1B0_SHIFT		= 0,
-	GPIO1B0_MASK		= 1,
+	GPIO1B0_MASK		= 1 << GPIO1B0_SHIFT,
 	GPIO1B0_GPIO		= 0,
 	GPIO1B0_HDMI_CEC,
 };
@@ -258,36 +257,36 @@ enum {
 /* GRF_GPIO1C_IOMUX */
 enum {
 	GPIO1C5_SHIFT		= 10,
-	GPIO1C5_MASK		= 3,
+	GPIO1C5_MASK		= 3 << GPIO1C5_SHIFT,
 	GPIO1C5_GPIO		= 0,
 	GPIO1C5_MMC0_D3,
 	GPIO1C5_JTAG_TMS,
 
 	GPIO1C4_SHIFT		= 8,
-	GPIO1C4_MASK		= 3,
+	GPIO1C4_MASK		= 3 << GPIO1C4_SHIFT,
 	GPIO1C4_GPIO		= 0,
 	GPIO1C4_MMC0_D2,
 	GPIO1C4_JTAG_TCK,
 
 	GPIO1C3_SHIFT		= 6,
-	GPIO1C3_MASK		= 3,
+	GPIO1C3_MASK		= 3 << GPIO1C3_SHIFT,
 	GPIO1C3_GPIO		= 0,
 	GPIO1C3_MMC0_D1,
 	GPIO1C3_UART2_SOUT,
 
 	GPIO1C2_SHIFT		= 4,
-	GPIO1C2_MASK		= 3,
+	GPIO1C2_MASK		= 3 << GPIO1C2_SHIFT ,
 	GPIO1C2_GPIO		= 0,
 	GPIO1C2_MMC0_D0,
 	GPIO1C2_UART2_SIN,
 
 	GPIO1C1_SHIFT		= 2,
-	GPIO1C1_MASK		= 1,
+	GPIO1C1_MASK		= 1 << GPIO1C1_SHIFT,
 	GPIO1C1_GPIO		= 0,
 	GPIO1C1_MMC0_DETN,
 
 	GPIO1C0_SHIFT		= 0,
-	GPIO1C0_MASK		= 1,
+	GPIO1C0_MASK		= 1 << GPIO1C0_SHIFT,
 	GPIO1C0_GPIO		= 0,
 	GPIO1C0_MMC0_CLKOUT,
 };
@@ -295,56 +294,56 @@ enum {
 /* GRF_GPIO1D_IOMUX */
 enum {
 	GPIO1D7_SHIFT		= 14,
-	GPIO1D7_MASK		= 3,
+	GPIO1D7_MASK		= 3 << GPIO1D7_SHIFT,
 	GPIO1D7_GPIO		= 0,
 	GPIO1D7_NAND_D7,
 	GPIO1D7_EMMC_D7,
 	GPIO1D7_SPI_CSN1,
 
 	GPIO1D6_SHIFT		= 12,
-	GPIO1D6_MASK		= 3,
+	GPIO1D6_MASK		= 3 << GPIO1D6_SHIFT,
 	GPIO1D6_GPIO		= 0,
 	GPIO1D6_NAND_D6,
 	GPIO1D6_EMMC_D6,
 	GPIO1D6_SPI_CSN0,
 
 	GPIO1D5_SHIFT		= 10,
-	GPIO1D5_MASK		= 3,
+	GPIO1D5_MASK		= 3 << GPIO1D5_SHIFT,
 	GPIO1D5_GPIO		= 0,
 	GPIO1D5_NAND_D5,
 	GPIO1D5_EMMC_D5,
 	GPIO1D5_SPI_TXD,
 
 	GPIO1D4_SHIFT		= 8,
-	GPIO1D4_MASK		= 3,
+	GPIO1D4_MASK		= 3 << GPIO1D4_SHIFT,
 	GPIO1D4_GPIO		= 0,
 	GPIO1D4_NAND_D4,
 	GPIO1D4_EMMC_D4,
 	GPIO1D4_SPI_RXD,
 
 	GPIO1D3_SHIFT		= 6,
-	GPIO1D3_MASK		= 3,
+	GPIO1D3_MASK		= 3 << GPIO1D3_SHIFT,
 	GPIO1D3_GPIO		= 0,
 	GPIO1D3_NAND_D3,
 	GPIO1D3_EMMC_D3,
 	GPIO1D3_SFC_SIO3,
 
 	GPIO1D2_SHIFT		= 4,
-	GPIO1D2_MASK		= 3,
+	GPIO1D2_MASK		= 3 << GPIO1D2_SHIFT,
 	GPIO1D2_GPIO		= 0,
 	GPIO1D2_NAND_D2,
 	GPIO1D2_EMMC_D2,
 	GPIO1D2_SFC_SIO2,
 
 	GPIO1D1_SHIFT		= 2,
-	GPIO1D1_MASK		= 3,
+	GPIO1D1_MASK		= 3 << GPIO1D1_SHIFT,
 	GPIO1D1_GPIO		= 0,
 	GPIO1D1_NAND_D1,
 	GPIO1D1_EMMC_D1,
 	GPIO1D1_SFC_SIO1,
 
 	GPIO1D0_SHIFT		= 0,
-	GPIO1D0_MASK		= 3,
+	GPIO1D0_MASK		= 3 << GPIO1D0_SHIFT,
 	GPIO1D0_GPIO		= 0,
 	GPIO1D0_NAND_D0,
 	GPIO1D0_EMMC_D0,
@@ -354,42 +353,42 @@ enum {
 /* GRF_GPIO2A_IOMUX */
 enum {
 	GPIO2A7_SHIFT		= 14,
-	GPIO2A7_MASK		= 1,
+	GPIO2A7_MASK		= 1 << GPIO2A7_SHIFT,
 	GPIO2A7_GPIO		= 0,
 	GPIO2A7_TESTCLK_OUT,
 
 	GPIO2A6_SHIFT		= 12,
-	GPIO2A6_MASK		= 1,
+	GPIO2A6_MASK		= 1 << GPIO2A6_SHIFT,
 	GPIO2A6_GPIO		= 0,
 	GPIO2A6_NAND_CS0,
 
 	GPIO2A4_SHIFT		= 8,
-	GPIO2A4_MASK		= 3,
+	GPIO2A4_MASK		= 3 << GPIO2A4_SHIFT,
 	GPIO2A4_GPIO		= 0,
 	GPIO2A4_NAND_RDY,
 	GPIO2A4_EMMC_CMD,
 	GPIO2A3_SFC_CLK,
 
 	GPIO2A3_SHIFT		= 6,
-	GPIO2A3_MASK		= 3,
+	GPIO2A3_MASK		= 3 << GPIO2A3_SHIFT,
 	GPIO2A3_GPIO		= 0,
 	GPIO2A3_NAND_RDN,
 	GPIO2A4_SFC_CSN1,
 
 	GPIO2A2_SHIFT		= 4,
-	GPIO2A2_MASK		= 3,
+	GPIO2A2_MASK		= 3 << GPIO2A2_SHIFT,
 	GPIO2A2_GPIO		= 0,
 	GPIO2A2_NAND_WRN,
 	GPIO2A4_SFC_CSN0,
 
 	GPIO2A1_SHIFT		= 2,
-	GPIO2A1_MASK		= 3,
+	GPIO2A1_MASK		= 3 << GPIO2A1_SHIFT,
 	GPIO2A1_GPIO		= 0,
 	GPIO2A1_NAND_CLE,
 	GPIO2A1_EMMC_CLKOUT,
 
 	GPIO2A0_SHIFT		= 0,
-	GPIO2A0_MASK		= 3,
+	GPIO2A0_MASK		= 3 << GPIO2A0_SHIFT,
 	GPIO2A0_GPIO		= 0,
 	GPIO2A0_NAND_ALE,
 	GPIO2A0_SPI_CLK,
@@ -398,28 +397,28 @@ enum {
 /* GRF_GPIO2B_IOMUX */
 enum {
 	GPIO2B7_SHIFT		= 14,
-	GPIO2B7_MASK		= 1,
+	GPIO2B7_MASK		= 1 << GPIO2B7_SHIFT,
 	GPIO2B7_GPIO		= 0,
 	GPIO2B7_MAC_RXER,
 
 	GPIO2B6_SHIFT		= 12,
-	GPIO2B6_MASK		= 3,
+	GPIO2B6_MASK		= 3 << GPIO2B6_SHIFT,
 	GPIO2B6_GPIO		= 0,
 	GPIO2B6_MAC_CLKOUT,
 	GPIO2B6_MAC_CLKIN,
 
 	GPIO2B5_SHIFT		= 10,
-	GPIO2B5_MASK		= 1,
+	GPIO2B5_MASK		= 1 << GPIO2B5_SHIFT,
 	GPIO2B5_GPIO		= 0,
 	GPIO2B5_MAC_TXEN,
 
 	GPIO2B4_SHIFT		= 8,
-	GPIO2B4_MASK		= 1,
+	GPIO2B4_MASK		= 1 << GPIO2B4_SHIFT,
 	GPIO2B4_GPIO		= 0,
 	GPIO2B4_MAC_MDIO,
 
 	GPIO2B2_SHIFT		= 4,
-	GPIO2B2_MASK		= 1,
+	GPIO2B2_MASK		= 1 << GPIO2B2_SHIFT,
 	GPIO2B2_GPIO		= 0,
 	GPIO2B2_MAC_CRS,
 };
@@ -427,43 +426,43 @@ enum {
 /* GRF_GPIO2C_IOMUX */
 enum {
 	GPIO2C7_SHIFT		= 14,
-	GPIO2C7_MASK		= 3,
+	GPIO2C7_MASK		= 3 << GPIO2C7_SHIFT,
 	GPIO2C7_GPIO		= 0,
 	GPIO2C7_UART1_SOUT,
 	GPIO2C7_TESTCLK_OUT1,
 
 	GPIO2C6_SHIFT		= 12,
-	GPIO2C6_MASK		= 1,
+	GPIO2C6_MASK		= 1 << GPIO2C6_SHIFT,
 	GPIO2C6_GPIO		= 0,
 	GPIO2C6_UART1_SIN,
 
 	GPIO2C5_SHIFT		= 10,
-	GPIO2C5_MASK		= 1,
+	GPIO2C5_MASK		= 1 << GPIO2C5_SHIFT,
 	GPIO2C5_GPIO		= 0,
 	GPIO2C5_I2C2_SCL,
 
 	GPIO2C4_SHIFT		= 8,
-	GPIO2C4_MASK		= 1,
+	GPIO2C4_MASK		= 1 << GPIO2C4_SHIFT,
 	GPIO2C4_GPIO		= 0,
 	GPIO2C4_I2C2_SDA,
 
 	GPIO2C3_SHIFT		= 6,
-	GPIO2C3_MASK		= 1,
+	GPIO2C3_MASK		= 1 << GPIO2C3_SHIFT,
 	GPIO2C3_GPIO		= 0,
 	GPIO2C3_MAC_TXD0,
 
 	GPIO2C2_SHIFT		= 4,
-	GPIO2C2_MASK		= 1,
+	GPIO2C2_MASK		= 1 << GPIO2C2_SHIFT,
 	GPIO2C2_GPIO		= 0,
 	GPIO2C2_MAC_TXD1,
 
 	GPIO2C1_SHIFT		= 2,
-	GPIO2C1_MASK		= 1,
+	GPIO2C1_MASK		= 1 << GPIO2C1_SHIFT,
 	GPIO2C1_GPIO		= 0,
 	GPIO2C1_MAC_RXD0,
 
 	GPIO2C0_SHIFT		= 0,
-	GPIO2C0_MASK		= 1,
+	GPIO2C0_MASK		= 1 << GPIO2C0_SHIFT,
 	GPIO2C0_GPIO		= 0,
 	GPIO2C0_MAC_RXD1,
 };
@@ -471,22 +470,22 @@ enum {
 /* GRF_GPIO2D_IOMUX */
 enum {
 	GPIO2D6_SHIFT		= 12,
-	GPIO2D6_MASK		= 1,
+	GPIO2D6_MASK		= 1 << GPIO2D6_SHIFT,
 	GPIO2D6_GPIO		= 0,
 	GPIO2D6_I2S_SDO1,
 
 	GPIO2D5_SHIFT		= 10,
-	GPIO2D5_MASK		= 1,
+	GPIO2D5_MASK		= 1 << GPIO2D5_SHIFT,
 	GPIO2D5_GPIO		= 0,
 	GPIO2D5_I2S_SDO2,
 
 	GPIO2D4_SHIFT		= 8,
-	GPIO2D4_MASK		= 1,
+	GPIO2D4_MASK		= 1 << GPIO2D4_SHIFT,
 	GPIO2D4_GPIO		= 0,
 	GPIO2D4_I2S_SDO3,
 
 	GPIO2D1_SHIFT		= 2,
-	GPIO2D1_MASK		= 1,
+	GPIO2D1_MASK		= 1 << GPIO2D1_SHIFT,
 	GPIO2D1_GPIO		= 0,
 	GPIO2D1_MAC_MDC,
 };
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
index 7d56b8ced0..fbc4a0d80f 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
@@ -813,7 +813,7 @@ enum {
 		(1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT),
 	RK3288_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
 	RK3288_TXCLK_DLY_ENA_GMAC_ENABLE =
-		(1 << RK3288_RXCLK_DLY_ENA_GMAC_SHIFT),
+		(1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT),
 
 	RK3288_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
 	RK3288_CLK_RX_DL_CFG_GMAC_MASK =
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3328.h b/arch/arm/include/asm/arch-rockchip/grf_rk3328.h
index 2776cefbb2..f0a0781d8d 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3328.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3328.h
@@ -131,4 +131,118 @@ struct rk3328_sgrf_regs {
 };
 check_member(rk3328_sgrf_regs, hdcp_key_access_mask, 0x2a0);
 
+enum {
+	/* GPIO0A_IOMUX */
+	GPIO0A5_SEL_SHIFT	= 10,
+	GPIO0A5_SEL_MASK	= 3 << GPIO0A5_SEL_SHIFT,
+	GPIO0A5_I2C3_SCL	= 2,
+
+	GPIO0A6_SEL_SHIFT	= 12,
+	GPIO0A6_SEL_MASK	= 3 << GPIO0A6_SEL_SHIFT,
+	GPIO0A6_I2C3_SDA	= 2,
+
+	GPIO0A7_SEL_SHIFT	= 14,
+	GPIO0A7_SEL_MASK	= 3 << GPIO0A7_SEL_SHIFT,
+	GPIO0A7_EMMC_DATA0	= 2,
+
+	/* GPIO0D_IOMUX*/
+	GPIO0D6_SEL_SHIFT	= 12,
+	GPIO0D6_SEL_MASK	= 3 << GPIO0D6_SEL_SHIFT,
+	GPIO0D6_GPIO		= 0,
+	GPIO0D6_SDMMC0_PWRENM1	= 3,
+
+	/* GPIO1A_IOMUX */
+	GPIO1A0_SEL_SHIFT	= 0,
+	GPIO1A0_SEL_MASK	= 0x3fff << GPIO1A0_SEL_SHIFT,
+	GPIO1A0_CARD_DATA_CLK_CMD_DETN	= 0x1555,
+
+	/* GPIO2A_IOMUX */
+	GPIO2A0_SEL_SHIFT	= 0,
+	GPIO2A0_SEL_MASK	= 3 << GPIO2A0_SEL_SHIFT,
+	GPIO2A0_UART2_TX_M1	= 1,
+
+	GPIO2A1_SEL_SHIFT	= 2,
+	GPIO2A1_SEL_MASK	= 3 << GPIO2A1_SEL_SHIFT,
+	GPIO2A1_UART2_RX_M1	= 1,
+
+	GPIO2A2_SEL_SHIFT	= 4,
+	GPIO2A2_SEL_MASK	= 3 << GPIO2A2_SEL_SHIFT,
+	GPIO2A2_PWM_IR		= 1,
+
+	GPIO2A4_SEL_SHIFT	= 8,
+	GPIO2A4_SEL_MASK	= 3 << GPIO2A4_SEL_SHIFT,
+	GPIO2A4_PWM_0		= 1,
+	GPIO2A4_I2C1_SDA,
+
+	GPIO2A5_SEL_SHIFT	= 10,
+	GPIO2A5_SEL_MASK	= 3 << GPIO2A5_SEL_SHIFT,
+	GPIO2A5_PWM_1		= 1,
+	GPIO2A5_I2C1_SCL,
+
+	GPIO2A6_SEL_SHIFT	= 12,
+	GPIO2A6_SEL_MASK	= 3 << GPIO2A6_SEL_SHIFT,
+	GPIO2A6_PWM_2		= 1,
+
+	GPIO2A7_SEL_SHIFT	= 14,
+	GPIO2A7_SEL_MASK	= 3 << GPIO2A7_SEL_SHIFT,
+	GPIO2A7_GPIO		= 0,
+	GPIO2A7_SDMMC0_PWRENM0,
+
+	/* GPIO2BL_IOMUX */
+	GPIO2BL0_SEL_SHIFT	= 0,
+	GPIO2BL0_SEL_MASK	= 0x3f << GPIO2BL0_SEL_SHIFT,
+	GPIO2BL0_SPI_CLK_TX_RX_M0	= 0x15,
+
+	GPIO2BL3_SEL_SHIFT	= 6,
+	GPIO2BL3_SEL_MASK	= 3 << GPIO2BL3_SEL_SHIFT,
+	GPIO2BL3_SPI_CSN0_M0	= 1,
+
+	GPIO2BL4_SEL_SHIFT	= 8,
+	GPIO2BL4_SEL_MASK	= 3 << GPIO2BL4_SEL_SHIFT,
+	GPIO2BL4_SPI_CSN1_M0	= 1,
+
+	GPIO2BL5_SEL_SHIFT	= 10,
+	GPIO2BL5_SEL_MASK	= 3 << GPIO2BL5_SEL_SHIFT,
+	GPIO2BL5_I2C2_SDA	= 1,
+
+	GPIO2BL6_SEL_SHIFT	= 12,
+	GPIO2BL6_SEL_MASK	= 3 << GPIO2BL6_SEL_SHIFT,
+	GPIO2BL6_I2C2_SCL	= 1,
+
+	/* GPIO2D_IOMUX */
+	GPIO2D0_SEL_SHIFT	= 0,
+	GPIO2D0_SEL_MASK	= 3 << GPIO2D0_SEL_SHIFT,
+	GPIO2D0_I2C0_SCL	= 1,
+
+	GPIO2D1_SEL_SHIFT	= 2,
+	GPIO2D1_SEL_MASK	= 3 << GPIO2D1_SEL_SHIFT,
+	GPIO2D1_I2C0_SDA	= 1,
+
+	GPIO2D4_SEL_SHIFT	= 8,
+	GPIO2D4_SEL_MASK	= 0xff << GPIO2D4_SEL_SHIFT,
+	GPIO2D4_EMMC_DATA1234	= 0xaa,
+
+	/* GPIO3C_IOMUX */
+	GPIO3C0_SEL_SHIFT	= 0,
+	GPIO3C0_SEL_MASK	= 0x3fff << GPIO3C0_SEL_SHIFT,
+	GPIO3C0_EMMC_DATA567_PWR_CLK_RSTN_CMD	= 0x2aaa,
+
+	/* COM_IOMUX */
+	IOMUX_SEL_UART2_SHIFT	= 0,
+	IOMUX_SEL_UART2_MASK	= 3 << IOMUX_SEL_UART2_SHIFT,
+	IOMUX_SEL_UART2_M0	= 0,
+	IOMUX_SEL_UART2_M1,
+
+	IOMUX_SEL_SPI_SHIFT	= 4,
+	IOMUX_SEL_SPI_MASK	= 3 << IOMUX_SEL_SPI_SHIFT,
+	IOMUX_SEL_SPI_M0	= 0,
+	IOMUX_SEL_SPI_M1,
+	IOMUX_SEL_SPI_M2,
+
+	IOMUX_SEL_SDMMC_SHIFT	= 7,
+	IOMUX_SEL_SDMMC_MASK	= 1 << IOMUX_SEL_SDMMC_SHIFT,
+	IOMUX_SEL_SDMMC_M0	= 0,
+	IOMUX_SEL_SDMMC_M1,
+};
+
 #endif	/* __SOC_ROCKCHIP_RK3328_GRF_H__ */
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
new file mode 100644
index 0000000000..3233dc306e
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
@@ -0,0 +1,440 @@
+/* (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+#ifndef _ASM_ARCH_GRF_RK3368_H
+#define _ASM_ARCH_GRF_RK3368_H
+
+#include <common.h>
+
+struct rk3368_grf {
+	u32 gpio1a_iomux;
+	u32 gpio1b_iomux;
+	u32 gpio1c_iomux;
+	u32 gpio1d_iomux;
+	u32 gpio2a_iomux;
+	u32 gpio2b_iomux;
+	u32 gpio2c_iomux;
+	u32 gpio2d_iomux;
+	u32 gpio3a_iomux;
+	u32 gpio3b_iomux;
+	u32 gpio3c_iomux;
+	u32 gpio3d_iomux;
+	u32 reserved[0x34];
+	u32 gpio1a_pull;
+	u32 gpio1b_pull;
+	u32 gpio1c_pull;
+	u32 gpio1d_pull;
+	u32 gpio2a_pull;
+	u32 gpio2b_pull;
+	u32 gpio2c_pull;
+	u32 gpio2d_pull;
+	u32 gpio3a_pull;
+	u32 gpio3b_pull;
+	u32 gpio3c_pull;
+	u32 gpio3d_pull;
+	u32 reserved1[0x34];
+	u32 gpio1a_drv;
+	u32 gpio1b_drv;
+	u32 gpio1c_drv;
+	u32 gpio1d_drv;
+	u32 gpio2a_drv;
+	u32 gpio2b_drv;
+	u32 gpio2c_drv;
+	u32 gpio2d_drv;
+	u32 gpio3a_drv;
+	u32 gpio3b_drv;
+	u32 gpio3c_drv;
+	u32 gpio3d_drv;
+	u32 reserved2[0x34];
+	u32 gpio1l_sr;
+	u32 gpio1h_sr;
+	u32 gpio2l_sr;
+	u32 gpio2h_sr;
+	u32 gpio3l_sr;
+	u32 gpio3h_sr;
+	u32 reserved3[0x1a];
+	u32 gpio_smt;
+	u32 reserved4[0x1f];
+	u32 soc_con0;
+	u32 soc_con1;
+	u32 soc_con2;
+	u32 soc_con3;
+	u32 soc_con4;
+	u32 soc_con5;
+	u32 soc_con6;
+	u32 soc_con7;
+	u32 soc_con8;
+	u32 soc_con9;
+	u32 soc_con10;
+	u32 soc_con11;
+	u32 soc_con12;
+	u32 soc_con13;
+	u32 soc_con14;
+	u32 soc_con15;
+	u32 soc_con16;
+	u32 soc_con17;
+};
+check_member(rk3368_grf, soc_con17, 0x444);
+
+struct rk3368_pmu_grf {
+	u32 gpio0a_iomux;
+	u32 gpio0b_iomux;
+	u32 gpio0c_iomux;
+	u32 gpio0d_iomux;
+	u32 gpio0a_pull;
+	u32 gpio0b_pull;
+	u32 gpio0c_pull;
+	u32 gpio0d_pull;
+	u32 gpio0a_drv;
+	u32 gpio0b_drv;
+	u32 gpio0c_drv;
+	u32 gpio0d_drv;
+	u32 gpio0l_sr;
+	u32 gpio0h_sr;
+};
+check_member(rk3368_pmu_grf, gpio0h_sr, 0x34);
+
+/*GRF_GPIO0C_IOMUX*/
+enum {
+	GPIO0C7_SHIFT		= 14,
+	GPIO0C7_MASK		= 3 << GPIO0C7_SHIFT,
+	GPIO0C7_GPIO		= 0,
+	GPIO0C7_LCDC_D19,
+	GPIO0C7_TRACE_D9,
+	GPIO0C7_UART1_RTSN,
+
+	GPIO0C6_SHIFT           = 12,
+	GPIO0C6_MASK            = 3 << GPIO0C6_SHIFT,
+	GPIO0C6_GPIO            = 0,
+	GPIO0C6_LCDC_D18,
+	GPIO0C6_TRACE_D8,
+	GPIO0C6_UART1_CTSN,
+
+	GPIO0C5_SHIFT           = 10,
+	GPIO0C5_MASK            = 3 << GPIO0C5_SHIFT,
+	GPIO0C5_GPIO            = 0,
+	GPIO0C5_LCDC_D17,
+	GPIO0C5_TRACE_D7,
+	GPIO0C5_UART1_SOUT,
+
+	GPIO0C4_SHIFT           = 8,
+	GPIO0C4_MASK            = 3 << GPIO0C4_SHIFT,
+	GPIO0C4_GPIO            = 0,
+	GPIO0C4_LCDC_D16,
+	GPIO0C4_TRACE_D6,
+	GPIO0C4_UART1_SIN,
+
+	GPIO0C3_SHIFT           = 6,
+	GPIO0C3_MASK            = 3 << GPIO0C3_SHIFT,
+	GPIO0C3_GPIO            = 0,
+	GPIO0C3_LCDC_D15,
+	GPIO0C3_TRACE_D5,
+	GPIO0C3_MCU_JTAG_TDO,
+
+	GPIO0C2_SHIFT           = 4,
+	GPIO0C2_MASK            = 3 << GPIO0C2_SHIFT,
+	GPIO0C2_GPIO            = 0,
+	GPIO0C2_LCDC_D14,
+	GPIO0C2_TRACE_D4,
+	GPIO0C2_MCU_JTAG_TDI,
+
+	GPIO0C1_SHIFT           = 2,
+	GPIO0C1_MASK            = 3 << GPIO0C1_SHIFT,
+	GPIO0C1_GPIO            = 0,
+	GPIO0C1_LCDC_D13,
+	GPIO0C1_TRACE_D3,
+	GPIO0C1_MCU_JTAG_TRTSN,
+
+	GPIO0C0_SHIFT           = 0,
+	GPIO0C0_MASK            = 3 << GPIO0C0_SHIFT,
+	GPIO0C0_GPIO            = 0,
+	GPIO0C0_LCDC_D12,
+	GPIO0C0_TRACE_D2,
+	GPIO0C0_MCU_JTAG_TDO,
+};
+
+/*GRF_GPIO0D_IOMUX*/
+enum {
+	GPIO0D7_SHIFT           = 14,
+	GPIO0D7_MASK            = 3 << GPIO0D7_SHIFT,
+	GPIO0D7_GPIO            = 0,
+	GPIO0D7_LCDC_DCLK,
+	GPIO0D7_TRACE_CTL,
+	GPIO0D7_PMU_DEBUG5,
+
+	GPIO0D6_SHIFT           = 12,
+	GPIO0D6_MASK            = 3 << GPIO0D6_SHIFT,
+	GPIO0D6_GPIO            = 0,
+	GPIO0D6_LCDC_DEN,
+	GPIO0D6_TRACE_CLK,
+	GPIO0D6_PMU_DEBUG4,
+
+	GPIO0D5_SHIFT           = 10,
+	GPIO0D5_MASK            = 3 << GPIO0D5_SHIFT,
+	GPIO0D5_GPIO            = 0,
+	GPIO0D5_LCDC_VSYNC,
+	GPIO0D5_TRACE_D15,
+	GPIO0D5_PMU_DEBUG3,
+
+	GPIO0D4_SHIFT           = 8,
+	GPIO0D4_MASK            = 3 << GPIO0D4_SHIFT,
+	GPIO0D4_GPIO            = 0,
+	GPIO0D4_LCDC_HSYNC,
+	GPIO0D4_TRACE_D14,
+	GPIO0D4_PMU_DEBUG2,
+
+	GPIO0D3_SHIFT           = 6,
+	GPIO0D3_MASK            = 3 << GPIO0D3_SHIFT,
+	GPIO0D3_GPIO            = 0,
+	GPIO0D3_LCDC_D23,
+	GPIO0D3_TRACE_D13,
+	GPIO0D3_UART4_SIN,
+
+	GPIO0D2_SHIFT           = 4,
+	GPIO0D2_MASK            = 3 << GPIO0D2_SHIFT,
+	GPIO0D2_GPIO            = 0,
+	GPIO0D2_LCDC_D22,
+	GPIO0D2_TRACE_D12,
+	GPIO0D2_UART4_SOUT,
+
+	GPIO0D1_SHIFT           = 2,
+	GPIO0D1_MASK            = 3 << GPIO0D1_SHIFT,
+	GPIO0D1_GPIO            = 0,
+	GPIO0D1_LCDC_D21,
+	GPIO0D1_TRACE_D11,
+	GPIO0D1_UART4_RTSN,
+
+	GPIO0D0_SHIFT           = 0,
+	GPIO0D0_MASK            = 3 << GPIO0D0_SHIFT,
+	GPIO0D0_GPIO            = 0,
+	GPIO0D0_LCDC_D20,
+	GPIO0D0_TRACE_D10,
+	GPIO0D0_UART4_CTSN,
+};
+
+/*GRF_GPIO2A_IOMUX*/
+enum {
+	GPIO2A7_SHIFT           = 14,
+	GPIO2A7_MASK            = 3 << GPIO2A7_SHIFT,
+	GPIO2A7_GPIO            = 0,
+	GPIO2A7_SDMMC0_D2,
+	GPIO2A7_JTAG_TCK,
+
+	GPIO2A6_SHIFT           = 12,
+	GPIO2A6_MASK            = 3 << GPIO2A6_SHIFT,
+	GPIO2A6_GPIO            = 0,
+	GPIO2A6_SDMMC0_D1,
+	GPIO2A6_UART2_SIN,
+
+	GPIO2A5_SHIFT           = 10,
+	GPIO2A5_MASK            = 3 << GPIO2A5_SHIFT,
+	GPIO2A5_GPIO            = 0,
+	GPIO2A5_SDMMC0_D0,
+	GPIO2A5_UART2_SOUT,
+
+	GPIO2A4_SHIFT           = 8,
+	GPIO2A4_MASK            = 3 << GPIO2A4_SHIFT,
+	GPIO2A4_GPIO            = 0,
+	GPIO2A4_FLASH_DQS,
+	GPIO2A4_EMMC_CLKO,
+
+	GPIO2A3_SHIFT           = 6,
+	GPIO2A3_MASK            = 3 << GPIO2A3_SHIFT,
+	GPIO2A3_GPIO            = 0,
+	GPIO2A3_FLASH_CSN3,
+	GPIO2A3_EMMC_RSTNO,
+
+	GPIO2A2_SHIFT           = 4,
+	GPIO2A2_MASK            = 3 << GPIO2A2_SHIFT,
+	GPIO2A2_GPIO           = 0,
+	GPIO2A2_FLASH_CSN2,
+
+	GPIO2A1_SHIFT           = 2,
+	GPIO2A1_MASK            = 3 << GPIO2A1_SHIFT,
+	GPIO2A1_GPIO            = 0,
+	GPIO2A1_FLASH_CSN1,
+
+	GPIO2A0_SHIFT           = 0,
+	GPIO2A0_MASK            = 3 << GPIO2A0_SHIFT,
+	GPIO2A0_GPIO            = 0,
+	GPIO2A0_FLASH_CSN0,
+};
+
+/*GRF_GPIO2D_IOMUX*/
+enum {
+	GPIO2D7_SHIFT           = 14,
+	GPIO2D7_MASK            = 3 << GPIO2D7_SHIFT,
+	GPIO2D7_GPIO            = 0,
+	GPIO2D7_SDIO0_D3,
+
+	GPIO2D6_SHIFT           = 12,
+	GPIO2D6_MASK            = 3 << GPIO2D6_SHIFT,
+	GPIO2D6_GPIO            = 0,
+	GPIO2D6_SDIO0_D2,
+
+	GPIO2D5_SHIFT           = 10,
+	GPIO2D5_MASK            = 3 << GPIO2D5_SHIFT,
+	GPIO2D5_GPIO            = 0,
+	GPIO2D5_SDIO0_D1,
+
+	GPIO2D4_SHIFT           = 8,
+	GPIO2D4_MASK            = 3 << GPIO2D4_SHIFT,
+	GPIO2D4_GPIO            = 0,
+	GPIO2D4_SDIO0_D0,
+
+	GPIO2D3_SHIFT           = 6,
+	GPIO2D3_MASK            = 3 << GPIO2D3_SHIFT,
+	GPIO2D3_GPIO            = 0,
+	GPIO2D3_UART0_RTS0,
+
+	GPIO2D2_SHIFT           = 4,
+	GPIO2D2_MASK            = 3 << GPIO2D2_SHIFT,
+	GPIO2D2_GPIO            = 0,
+	GPIO2D2_UART0_CTS0,
+
+	GPIO2D1_SHIFT           = 2,
+	GPIO2D1_MASK            = 3 << GPIO2D1_SHIFT,
+	GPIO2D1_GPIO            = 0,
+	GPIO2D1_UART0_SOUT,
+
+	GPIO2D0_SHIFT           = 0,
+	GPIO2D0_MASK            = 3 << GPIO2D0_SHIFT,
+	GPIO2D0_GPIO            = 0,
+	GPIO2D0_UART0_SIN,
+};
+
+/*GRF_GPIO3C_IOMUX*/
+enum {
+	GPIO3C7_SHIFT           = 14,
+	GPIO3C7_MASK            = 3 << GPIO3C7_SHIFT,
+	GPIO3C7_GPIO            = 0,
+	GPIO3C7_EDPHDMI_CECINOUT,
+	GPIO3C7_ISP_FLASHTRIGIN,
+
+	GPIO3C6_SHIFT           = 12,
+	GPIO3C6_MASK            = 3 << GPIO3C6_SHIFT,
+	GPIO3C6_GPIO            = 0,
+	GPIO3C6_MAC_CLK,
+	GPIO3C6_ISP_SHUTTERTRIG,
+
+	GPIO3C5_SHIFT           = 10,
+	GPIO3C5_MASK            = 3 << GPIO3C5_SHIFT,
+	GPIO3C5_GPIO            = 0,
+	GPIO3C5_MAC_RXER,
+	GPIO3C5_ISP_PRELIGHTTRIG,
+
+	GPIO3C4_SHIFT           = 8,
+	GPIO3C4_MASK            = 3 << GPIO3C4_SHIFT,
+	GPIO3C4_GPIO            = 0,
+	GPIO3C4_MAC_RXDV,
+	GPIO3C4_ISP_FLASHTRIGOUT,
+
+	GPIO3C3_SHIFT           = 6,
+	GPIO3C3_MASK            = 3 << GPIO3C3_SHIFT,
+	GPIO3C3_GPIO            = 0,
+	GPIO3C3_MAC_RXDV,
+	GPIO3C3_EMMC_RSTNO,
+
+	GPIO3C2_SHIFT           = 4,
+	GPIO3C2_MASK            = 3 << GPIO3C2_SHIFT,
+	GPIO3C2_MAC_MDC            = 0,
+	GPIO3C2_ISP_SHUTTEREN,
+
+	GPIO3C1_SHIFT           = 2,
+	GPIO3C1_MASK            = 3 << GPIO3C1_SHIFT,
+	GPIO3C1_GPIO            = 0,
+	GPIO3C1_MAC_RXD2,
+	GPIO3C1_UART3_RTSN,
+
+	GPIO3C0_SHIFT           = 0,
+	GPIO3C0_MASK            = 3 << GPIO3C0_SHIFT,
+	GPIO3C0_GPIO            = 0,
+	GPIO3C0_MAC_RXD1,
+	GPIO3C0_UART3_CTSN,
+	GPIO3C0_GPS_RFCLK,
+};
+
+/*GRF_GPIO3D_IOMUX*/
+enum {
+	GPIO3D7_SHIFT           = 14,
+	GPIO3D7_MASK            = 3 << GPIO3D7_SHIFT,
+	GPIO3D7_GPIO            = 0,
+	GPIO3D7_SC_VCC18V,
+	GPIO3D7_I2C2_SDA,
+	GPIO3D7_GPUJTAG_TCK,
+
+	GPIO3D6_SHIFT           = 12,
+	GPIO3D6_MASK            = 3 << GPIO3D6_SHIFT,
+	GPIO3D6_GPIO            = 0,
+	GPIO3D6_IR_TX,
+	GPIO3D6_UART3_SOUT,
+	GPIO3D6_PWM3,
+
+	GPIO3D5_SHIFT           = 10,
+	GPIO3D5_MASK            = 3 << GPIO3D5_SHIFT,
+	GPIO3D5_GPIO            = 0,
+	GPIO3D5_IR_RX,
+	GPIO3D5_UART3_SIN,
+
+	GPIO3D4_SHIFT           = 8,
+	GPIO3D4_MASK            = 3 << GPIO3D4_SHIFT,
+	GPIO3D4_GPIO            = 0,
+	GPIO3D4_MAC_TXCLKOUT,
+	GPIO3D4_SPI1_CSN1,
+
+	GPIO3D3_SHIFT           = 6,
+	GPIO3D3_MASK            = 3 << GPIO3D3_SHIFT,
+	GPIO3D3_GPIO            = 0,
+	GPIO3D3_HDMII2C_SCL,
+	GPIO3D3_I2C5_SCL,
+
+	GPIO3D2_SHIFT           = 4,
+	GPIO3D2_MASK            = 3 << GPIO3D2_SHIFT,
+	GPIO3D2_GPIO            = 0,
+	GPIO3D2_HDMII2C_SDA,
+	GPIO3D2_I2C5_SDA,
+
+	GPIO3D1_SHIFT           = 2,
+	GPIO3D1_MASK            = 3 << GPIO3D1_SHIFT,
+	GPIO3D1_GPIO            = 0,
+	GPIO3D1_MAC_RXCLKIN,
+	GPIO3D1_I2C4_SCL,
+
+	GPIO3D0_SHIFT           = 0,
+	GPIO3D0_MASK            = 3 << GPIO3D0_SHIFT,
+	GPIO3D0_GPIO            = 0,
+	GPIO3D0_MAC_MDIO,
+	GPIO3D0_I2C4_SDA,
+};
+
+/*GRF_SOC_CON11/12/13*/
+enum {
+	MCU_SRAM_BASE_BIT27_BIT12_SHIFT	= 0,
+	MCU_SRAM_BASE_BIT27_BIT12_MASK	= GENMASK(15, 0),
+};
+
+/*GRF_SOC_CON12*/
+enum {
+	MCU_EXSRAM_BASE_BIT27_BIT12_SHIFT  = 0,
+	MCU_EXSRAM_BASE_BIT27_BIT12_MASK   = GENMASK(15, 0),
+};
+
+/*GRF_SOC_CON13*/
+enum {
+	MCU_EXPERI_BASE_BIT27_BIT12_SHIFT  = 0,
+	MCU_EXPERI_BASE_BIT27_BIT12_MASK   = GENMASK(15, 0),
+};
+
+/*GRF_SOC_CON14*/
+enum {
+	MCU_EXPERI_BASE_BIT31_BIT28_SHIFT	= 12,
+	MCU_EXPERI_BASE_BIT31_BIT28_MASK	= GENMASK(15, 12),
+	MCU_EXSRAM_BASE_BIT31_BIT28_SHIFT	= 8,
+	MCU_EXSRAM_BASE_BIT31_BIT28_MASK	= GENMASK(11, 8),
+	MCU_SRAM_BASE_BIT31_BIT28_SHIFT		= 4,
+	MCU_SRAM_BASE_BIT31_BIT28_MASK		= GENMASK(7, 4),
+	MCU_CODE_BASE_BIT31_BIT28_SHIFT		= 0,
+	MCU_CODE_BASE_BIT31_BIT28_MASK		= GENMASK(3, 0),
+};
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
index eda99560ed..8d21eb7bee 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
@@ -534,6 +534,9 @@ enum {
 	GRF_DSI0_VOP_SEL_MASK   = 1 << GRF_DSI0_VOP_SEL_SHIFT,
 	GRF_DSI0_VOP_SEL_B      = 0,
 	GRF_DSI0_VOP_SEL_L      = 1,
+	GRF_RK3399_HDMI_VOP_SEL_MASK = 1 << 6,
+	GRF_RK3399_HDMI_VOP_SEL_B = 0 << 6,
+	GRF_RK3399_HDMI_VOP_SEL_L = 1 << 6,
 
 	/* GRF_SOC_CON22 */
 	GRF_DPHY_TX0_RXMODE_SHIFT = 0,
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rv1108.h b/arch/arm/include/asm/arch-rockchip/grf_rv1108.h
new file mode 100644
index 0000000000..c816a5bf8f
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/grf_rv1108.h
@@ -0,0 +1,509 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+#ifndef _ASM_ARCH_GRF_RV1108_H
+#define _ASM_ARCH_GRF_RV1108_H
+
+#include <common.h>
+
+struct rv1108_grf {
+	u32 reserved[4];
+	u32 gpio1a_iomux;
+	u32 gpio1b_iomux;
+	u32 gpio1c_iomux;
+	u32 gpio1d_iomux;
+	u32 gpio2a_iomux;
+	u32 gpio2b_iomux;
+	u32 gpio2c_iomux;
+	u32 gpio2d_iomux;
+	u32 gpio3a_iomux;
+	u32 gpio3b_iomux;
+	u32 gpio3c_iomux;
+	u32 gpio3d_iomux;
+	u32 reserved1[52];
+	u32 gpio1a_pull;
+	u32 gpio1b_pull;
+	u32 gpio1c_pull;
+	u32 gpio1d_pull;
+	u32 gpio2a_pull;
+	u32 gpio2b_pull;
+	u32 gpio2c_pull;
+	u32 gpio2d_pull;
+	u32 gpio3a_pull;
+	u32 gpio3b_pull;
+	u32 gpio3c_pull;
+	u32 gpio3d_pull;
+	u32 reserved2[52];
+	u32 gpio1a_drv;
+	u32 gpio1b_drv;
+	u32 gpio1c_drv;
+	u32 gpio1d_drv;
+	u32 gpio2a_drv;
+	u32 gpio2b_drv;
+	u32 gpio2c_drv;
+	u32 gpio2d_drv;
+	u32 gpio3a_drv;
+	u32 gpio3b_drv;
+	u32 gpio3c_drv;
+	u32 gpio3d_drv;
+	u32 reserved3[50];
+	u32 gpio1l_sr;
+	u32 gpio1h_sr;
+	u32 gpio2l_sr;
+	u32 gpio2h_sr;
+	u32 gpio3l_sr;
+	u32 gpio3h_sr;
+	u32 reserved4[26];
+	u32 gpio1l_smt;
+	u32 gpio1h_smt;
+	u32 gpio2l_smt;
+	u32 gpio2h_smt;
+	u32 gpio3l_smt;
+	u32 gpio3h_smt;
+	u32 reserved5[24];
+	u32 soc_con0;
+	u32 soc_con1;
+	u32 soc_con2;
+	u32 soc_con3;
+	u32 soc_con4;
+	u32 soc_con5;
+	u32 soc_con6;
+	u32 soc_con7;
+	u32 soc_con8;
+	u32 soc_con9;
+	u32 soc_con10;
+	u32 soc_con11;
+	u32 reserved6[20];
+	u32 soc_status0;
+	u32 soc_status1;
+	u32 reserved7[30];
+	u32 cpu_con0;
+	u32 cpu_con1;
+	u32 reserved8[30];
+	u32 os_reg0;
+	u32 os_reg1;
+	u32 os_reg2;
+	u32 os_reg3;
+	u32 reserved9[29];
+	u32 ddr_status;
+	u32 reserved10[30];
+	u32 sig_det_con;
+	u32 reserved11[3];
+	u32 sig_det_status;
+	u32 reserved12[3];
+	u32 sig_det_clr;
+	u32 reserved13[23];
+	u32 host_con0;
+	u32 host_con1;
+	u32 reserved14[2];
+	u32 dma_con0;
+	u32 dma_con1;
+	u32 reserved15[539];
+	u32 uoc_status;
+	u32 host_status;
+	u32 gmac_con0;
+	u32 chip_id;
+};
+check_member(rv1108_grf, chip_id, 0xf90);
+
+/* GRF_GPIO1B_IOMUX */
+enum {
+	GPIO1B7_SHIFT		= 14,
+	GPIO1B7_MASK		= 3 << GPIO1B7_SHIFT,
+	GPIO1B7_GPIO		= 0,
+	GPIO1B7_LCDC_D12,
+	GPIO1B7_I2S_SDIO2_M0,
+	GPIO1B7_GMAC_RXDV,
+
+	GPIO1B6_SHIFT		= 12,
+	GPIO1B6_MASK		= 3 << GPIO1B6_SHIFT,
+	GPIO1B6_GPIO		= 0,
+	GPIO1B6_LCDC_D13,
+	GPIO1B6_I2S_LRCLKTX_M0,
+	GPIO1B6_GMAC_RXD1,
+
+	GPIO1B5_SHIFT		= 10,
+	GPIO1B5_MASK		= 3 << GPIO1B5_SHIFT,
+	GPIO1B5_GPIO		= 0,
+	GPIO1B5_LCDC_D14,
+	GPIO1B5_I2S_SDIO1_M0,
+	GPIO1B5_GMAC_RXD0,
+
+	GPIO1B4_SHIFT		= 8,
+	GPIO1B4_MASK		= 3 << GPIO1B4_SHIFT,
+	GPIO1B4_GPIO		= 0,
+	GPIO1B4_LCDC_D15,
+	GPIO1B4_I2S_MCLK_M0,
+	GPIO1B4_GMAC_TXEN,
+
+	GPIO1B3_SHIFT		= 6,
+	GPIO1B3_MASK		= 3 << GPIO1B3_SHIFT,
+	GPIO1B3_GPIO		= 0,
+	GPIO1B3_LCDC_D16,
+	GPIO1B3_I2S_SCLK_M0,
+	GPIO1B3_GMAC_TXD1,
+
+	GPIO1B2_SHIFT		= 4,
+	GPIO1B2_MASK		= 3 << GPIO1B2_SHIFT,
+	GPIO1B2_GPIO		= 0,
+	GPIO1B2_LCDC_D17,
+	GPIO1B2_I2S_SDIO_M0,
+	GPIO1B2_GMAC_TXD0,
+
+	GPIO1B1_SHIFT		= 2,
+	GPIO1B1_MASK		= 3 << GPIO1B1_SHIFT,
+	GPIO1B1_GPIO		= 0,
+	GPIO1B1_LCDC_D9,
+	GPIO1B1_PWM7,
+
+	GPIO1B0_SHIFT		= 0,
+	GPIO1B0_MASK		= 3,
+	GPIO1B0_GPIO		= 0,
+	GPIO1B0_LCDC_D8,
+	GPIO1B0_PWM6,
+};
+
+/* GRF_GPIO1C_IOMUX */
+enum {
+	GPIO1C7_SHIFT		= 14,
+	GPIO1C7_MASK		= 3 << GPIO1C7_SHIFT,
+	GPIO1C7_GPIO		= 0,
+	GPIO1C7_CIF_D5,
+	GPIO1C7_I2S_SDIO2_M1,
+
+	GPIO1C6_SHIFT		= 12,
+	GPIO1C6_MASK		= 3 << GPIO1C6_SHIFT,
+	GPIO1C6_GPIO		= 0,
+	GPIO1C6_CIF_D4,
+	GPIO1C6_I2S_LRCLKTX_M1,
+
+	GPIO1C5_SHIFT		= 10,
+	GPIO1C5_MASK		= 3 << GPIO1C5_SHIFT,
+	GPIO1C5_GPIO		= 0,
+	GPIO1C5_LCDC_CLK,
+	GPIO1C5_GMAC_CLK,
+
+	GPIO1C4_SHIFT		= 8,
+	GPIO1C4_MASK		= 3 << GPIO1C4_SHIFT,
+	GPIO1C4_GPIO		= 0,
+	GPIO1C4_LCDC_HSYNC,
+	GPIO1C4_GMAC_MDC,
+
+	GPIO1C3_SHIFT		= 6,
+	GPIO1C3_MASK		= 3 << GPIO1C3_SHIFT,
+	GPIO1C3_GPIO		= 0,
+	GPIO1C3_LCDC_VSYNC,
+	GPIO1C3_GMAC_MDIO,
+
+	GPIO1C2_SHIFT		= 4,
+	GPIO1C2_MASK		= 3 << GPIO1C2_SHIFT,
+	GPIO1C2_GPIO		= 0,
+	GPIO1C2_LCDC_EN,
+	GPIO1C2_I2S_SDIO3_M0,
+	GPIO1C2_GMAC_RXER,
+
+	GPIO1C1_SHIFT		= 2,
+	GPIO1C1_MASK		= 3 << GPIO1C1_SHIFT,
+	GPIO1C1_GPIO		= 0,
+	GPIO1C1_LCDC_D10,
+	GPIO1C1_I2S_SDI_M0,
+	GPIO1C1_PWM4,
+
+	GPIO1C0_SHIFT           = 0,
+	GPIO1C0_MASK		= 3,
+	GPIO1C0_GPIO		= 0,
+	GPIO1C0_LCDC_D11,
+	GPIO1C0_I2S_LRCLKRX_M0,
+};
+
+/* GRF_GPIO1D_OIMUX */
+enum {
+	GPIO1D7_SHIFT		= 14,
+	GPIO1D7_MASK		= 3 << GPIO1D7_SHIFT,
+	GPIO1D7_GPIO		= 0,
+	GPIO1D7_HDMI_CEC,
+	GPIO1D7_DSP_RTCK,
+
+	GPIO1D6_SHIFT		= 12,
+	GPIO1D6_MASK		= 1 << GPIO1D6_SHIFT,
+	GPIO1D6_GPIO		= 0,
+	GPIO1D6_HDMI_HPD_M0,
+
+	GPIO1D5_SHIFT		= 10,
+	GPIO1D5_MASK		= 3 << GPIO1D5_SHIFT,
+	GPIO1D5_GPIO		= 0,
+	GPIO1D5_UART2_RTSN,
+	GPIO1D5_HDMI_SDA_M0,
+
+	GPIO1D4_SHIFT		= 8,
+	GPIO1D4_MASK		= 3 << GPIO1D4_SHIFT,
+	GPIO1D4_GPIO		= 0,
+	GPIO1D4_UART2_CTSN,
+	GPIO1D4_HDMI_SCL_M0,
+
+	GPIO1D3_SHIFT		= 6,
+	GPIO1D3_MASK		= 3 << GPIO1D3_SHIFT,
+	GPIO1D3_GPIO		= 0,
+	GPIO1D3_UART0_SOUT,
+	GPIO1D3_SPI_TXD_M0,
+
+	GPIO1D2_SHIFT		= 4,
+	GPIO1D2_MASK		= 3 << GPIO1D2_SHIFT,
+	GPIO1D2_GPIO		= 0,
+	GPIO1D2_UART0_SIN,
+	GPIO1D2_SPI_RXD_M0,
+	GPIO1D2_DSP_TDI,
+
+	GPIO1D1_SHIFT		= 2,
+	GPIO1D1_MASK		= 3 << GPIO1D1_SHIFT,
+	GPIO1D1_GPIO		= 0,
+	GPIO1D1_UART0_RTSN,
+	GPIO1D1_SPI_CSN0_M0,
+	GPIO1D1_DSP_TMS,
+
+	GPIO1D0_SHIFT		= 0,
+	GPIO1D0_MASK		= 3,
+	GPIO1D0_GPIO		= 0,
+	GPIO1D0_UART0_CTSN,
+	GPIO1D0_SPI_CLK_M0,
+	GPIO1D0_DSP_TCK,
+};
+
+/* GRF_GPIO2A_IOMUX */
+enum {
+	GPIO2A7_SHIFT		= 14,
+	GPIO2A7_MASK		= 3 << GPIO2A7_SHIFT,
+	GPIO2A7_GPIO		= 0,
+	GPIO2A7_FLASH_D7,
+	GPIO2A7_EMMC_D7,
+
+	GPIO2A6_SHIFT		= 12,
+	GPIO2A6_MASK		= 3 << GPIO2A6_SHIFT,
+	GPIO2A6_GPIO		= 0,
+	GPIO2A6_FLASH_D6,
+	GPIO2A6_EMMC_D6,
+
+	GPIO2A5_SHIFT           = 10,
+	GPIO2A5_MASK            = 3 << GPIO2A5_SHIFT,
+	GPIO2A5_GPIO            = 0,
+	GPIO2A5_FLASH_D5,
+	GPIO2A5_EMMC_D5,
+
+	GPIO2A4_SHIFT           = 8,
+	GPIO2A4_MASK            = 3 << GPIO2A4_SHIFT,
+	GPIO2A4_GPIO            = 0,
+	GPIO2A4_FLASH_D4,
+	GPIO2A4_EMMC_D4,
+
+	GPIO2A3_SHIFT           = 6,
+	GPIO2A3_MASK            = 3 << GPIO2A3_SHIFT,
+	GPIO2A3_GPIO            = 0,
+	GPIO2A3_FLASH_D3,
+	GPIO2A3_EMMC_D3,
+	GPIO2A3_SFC_HOLD_IO3,
+
+	GPIO2A2_SHIFT           = 4,
+	GPIO2A2_MASK            = 3 << GPIO2A2_SHIFT,
+	GPIO2A2_GPIO            = 0,
+	GPIO2A2_FLASH_D2,
+	GPIO2A2_EMMC_D2,
+	GPIO2A2_SFC_WP_IO2,
+
+	GPIO2A1_SHIFT           = 2,
+	GPIO2A1_MASK            = 3 << GPIO2A1_SHIFT,
+	GPIO2A1_GPIO            = 0,
+	GPIO2A1_FLASH_D1,
+	GPIO2A1_EMMC_D1,
+	GPIO2A1_SFC_SO_IO1,
+
+	GPIO2A0_SHIFT           = 0,
+	GPIO2A0_MASK            = 3 << GPIO2A0_SHIFT,
+	GPIO2A0_GPIO            = 0,
+	GPIO2A0_FLASH_D0,
+	GPIO2A0_EMMC_D0,
+	GPIO2A0_SFC_SI_IO0,
+};
+
+/* GRF_GPIO2D_IOMUX */
+enum {
+	GPIO2B7_SHIFT		= 14,
+	GPIO2B7_MASK		= 3 << GPIO2B7_SHIFT,
+	GPIO2B7_GPIO		= 0,
+	GPIO2B7_FLASH_CS1,
+	GPIO2B7_SFC_CLK,
+
+	GPIO2B6_SHIFT           = 12,
+	GPIO2B6_MASK            = 1 << GPIO2B6_SHIFT,
+	GPIO2B6_GPIO            = 0,
+	GPIO2B6_EMMC_CLKO,
+
+	GPIO2B5_SHIFT           = 10,
+	GPIO2B5_MASK            = 1 << GPIO2B5_SHIFT,
+	GPIO2B5_GPIO            = 0,
+	GPIO2B5_FLASH_CS0,
+
+	GPIO2B4_SHIFT           = 8,
+	GPIO2B4_MASK            = 3 << GPIO2B4_SHIFT,
+	GPIO2B4_GPIO            = 0,
+	GPIO2B4_FLASH_RDY,
+	GPIO2B4_EMMC_CMD,
+	GPIO2B4_SFC_CSN0,
+
+	GPIO2B3_SHIFT           = 6,
+	GPIO2B3_MASK            = 1 << GPIO2B3_SHIFT,
+	GPIO2B3_GPIO            = 0,
+	GPIO2B3_FLASH_RDN,
+
+	GPIO2B2_SHIFT           = 4,
+	GPIO2B2_MASK            = 1 << GPIO2B2_SHIFT,
+	GPIO2B2_GPIO            = 0,
+	GPIO2B2_FLASH_WRN,
+
+	GPIO2B1_SHIFT           = 2,
+	GPIO2B1_MASK            = 1 << GPIO2B1_SHIFT,
+	GPIO2B1_GPIO            = 0,
+	GPIO2B1_FLASH_CLE,
+
+	GPIO2B0_SHIFT           = 0,
+	GPIO2B0_MASK            = 1 << GPIO2B0_SHIFT,
+	GPIO2B0_GPIO            = 0,
+	GPIO2B0_FLASH_ALE,
+};
+
+/* GRF_GPIO2D_IOMUX */
+enum {
+	GPIO2D7_SHIFT		= 14,
+	GPIO2D7_MASK		= 1 << GPIO2D7_SHIFT,
+	GPIO2D7_GPIO		= 0,
+	GPIO2D7_SDIO_D0,
+
+	GPIO2D6_SHIFT		= 12,
+	GPIO2D6_MASK		= 1 << GPIO2D6_SHIFT,
+	GPIO2D6_GPIO		= 0,
+	GPIO2D6_SDIO_CMD,
+
+	GPIO2D5_SHIFT		= 10,
+	GPIO2D5_MASK		= 1 << GPIO2D5_SHIFT,
+	GPIO2D5_GPIO		= 0,
+	GPIO2D5_SDIO_CLKO,
+
+	GPIO2D4_SHIFT		= 8,
+	GPIO2D4_MASK		= 1 << GPIO2D4_SHIFT,
+	GPIO2D4_GPIO		= 0,
+	GPIO2D4_I2C1_SCL,
+
+	GPIO2D3_SHIFT		= 6,
+	GPIO2D3_MASK		= 1 << GPIO2D3_SHIFT,
+	GPIO2D3_GPIO		= 0,
+	GPIO2D3_I2C1_SDA,
+
+	GPIO2D2_SHIFT		= 4,
+	GPIO2D2_MASK		= 3 << GPIO2D2_SHIFT,
+	GPIO2D2_GPIO		= 0,
+	GPIO2D2_UART2_SOUT_M0,
+	GPIO2D2_JTAG_TCK,
+
+	GPIO2D1_SHIFT		= 2,
+	GPIO2D1_MASK		= 3 << GPIO2D1_SHIFT,
+	GPIO2D1_GPIO		= 0,
+	GPIO2D1_UART2_SIN_M0,
+	GPIO2D1_JTAG_TMS,
+	GPIO2D1_DSP_TMS,
+
+	GPIO2D0_SHIFT		= 0,
+	GPIO2D0_MASK		= 3,
+	GPIO2D0_GPIO		= 0,
+	GPIO2D0_UART0_CTSN,
+	GPIO2D0_SPI_CLK_M0,
+	GPIO2D0_DSP_TCK,
+};
+
+/* GRF_GPIO3A_IOMUX */
+enum {
+	GPIO3A7_SHIFT		= 14,
+	GPIO3A7_MASK		= 1 << GPIO3A7_SHIFT,
+	GPIO3A7_GPIO		= 0,
+
+	GPIO3A6_SHIFT		= 12,
+	GPIO3A6_MASK		= 1 << GPIO3A6_SHIFT,
+	GPIO3A6_GPIO		= 0,
+	GPIO3A6_UART1_SOUT,
+
+	GPIO3A5_SHIFT		= 10,
+	GPIO3A5_MASK		= 1 << GPIO3A5_SHIFT,
+	GPIO3A5_GPIO		= 0,
+	GPIO3A5_UART1_SIN,
+
+	GPIO3A4_SHIFT		= 8,
+	GPIO3A4_MASK		= 1 << GPIO3A4_SHIFT,
+	GPIO3A4_GPIO		= 0,
+	GPIO3A4_UART1_CTSN,
+
+	GPIO3A3_SHIFT		= 6,
+	GPIO3A3_MASK		= 1 << GPIO3A3_SHIFT,
+	GPIO3A3_GPIO		= 0,
+	GPIO3A3_UART1_RTSN,
+
+	GPIO3A2_SHIFT		= 4,
+	GPIO3A2_MASK		= 1 << GPIO3A2_SHIFT,
+	GPIO3A2_GPIO		= 0,
+	GPIO3A2_SDIO_D3,
+
+	GPIO3A1_SHIFT		= 2,
+	GPIO3A1_MASK		= 1 << GPIO3A1_SHIFT,
+	GPIO3A1_GPIO		= 0,
+	GPIO3A1_SDIO_D2,
+
+	GPIO3A0_SHIFT		= 0,
+	GPIO3A0_MASK		= 1,
+	GPIO3A0_GPIO		= 0,
+	GPIO3A0_SDIO_D1,
+};
+
+/* GRF_GPIO3C_IOMUX */
+enum {
+	GPIO3C7_SHIFT		= 14,
+	GPIO3C7_MASK		= 1 << GPIO3C7_SHIFT,
+	GPIO3C7_GPIO		= 0,
+	GPIO3C7_CIF_CLKI,
+
+	GPIO3C6_SHIFT		= 12,
+	GPIO3C6_MASK		= 1 << GPIO3C6_SHIFT,
+	GPIO3C6_GPIO		= 0,
+	GPIO3C6_CIF_VSYNC,
+
+	GPIO3C5_SHIFT		= 10,
+	GPIO3C5_MASK		= 1 << GPIO3C5_SHIFT,
+	GPIO3C5_GPIO		= 0,
+	GPIO3C5_SDMMC_CMD,
+
+	GPIO3C4_SHIFT		= 8,
+	GPIO3C4_MASK		= 1 << GPIO3C4_SHIFT,
+	GPIO3C4_GPIO		= 0,
+	GPIO3C4_SDMMC_CLKO,
+
+	GPIO3C3_SHIFT		= 6,
+	GPIO3C3_MASK		= 3 << GPIO3C3_SHIFT,
+	GPIO3C3_GPIO		= 0,
+	GPIO3C3_SDMMC_D0,
+	GPIO3C3_UART2_SOUT_M1,
+
+	GPIO3C2_SHIFT		= 4,
+	GPIO3C2_MASK		= 3 << GPIO3C2_SHIFT,
+	GPIO3C2_GPIO		= 0,
+	GPIO3C2_SDMMC_D1,
+	GPIO3C2_UART2_SIN_M1,
+
+	GPIOC1_SHIFT		= 2,
+	GPIOC1_MASK		= 1 << GPIOC1_SHIFT,
+	GPIOC1_GPIO		= 0,
+	GPIOC1_SDMMC_D2,
+
+	GPIOC0_SHIFT		= 0,
+	GPIOC0_MASK		= 1,
+	GPIO3C0_GPIO		= 0,
+	GPIO3C0_SDMMC_D3,
+};
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/periph.h b/arch/arm/include/asm/arch-rockchip/periph.h
index 8018d47348..9f4bc2e107 100644
--- a/arch/arm/include/asm/arch-rockchip/periph.h
+++ b/arch/arm/include/asm/arch-rockchip/periph.h
@@ -42,6 +42,7 @@ enum periph_id {
 	PERIPH_ID_SDMMC2,
 	PERIPH_ID_HDMI,
 	PERIPH_ID_GMAC,
+	PERIPH_ID_SFC,
 
 	PERIPH_ID_COUNT,
 
diff --git a/arch/arm/include/asm/arch-rockchip/vop_rk3288.h b/arch/arm/include/asm/arch-rockchip/vop_rk3288.h
index d5599ec335..21e59beb89 100644
--- a/arch/arm/include/asm/arch-rockchip/vop_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/vop_rk3288.h
@@ -197,9 +197,20 @@ enum vop_modes {
 #define V_DSP_DEN_POL(x)               (((x) & 1) << 6)
 #define V_DSP_VSYNC_POL(x)             (((x) & 1) << 5)
 #define V_DSP_HSYNC_POL(x)             (((x) & 1) << 4)
+#define V_DSP_PIN_POL(x)               (((x) & 0xf) << 4)
 #define V_DSP_OUT_MODE(x)              ((x) & 0xf)
 
 /* VOP_DSP_CTRL1 */
+#define V_RK3399_DSP_MIPI_POL(x)       ((x) << 28)
+#define V_RK3399_DSP_EDP_POL(x)        ((x) << 24)
+#define V_RK3399_DSP_HDMI_POL(x)       ((x) << 20)
+#define V_RK3399_DSP_LVDS_POL(x)       ((x) << 16)
+
+#define M_RK3399_DSP_MIPI_POL          (V_RK3399_DSP_MIPI_POL(0xf))
+#define M_RK3399_DSP_EDP_POL           (V_RK3399_DSP_EDP_POL(0xf))
+#define M_RK3399_DSP_HDMI_POL          (V_RK3399_DSP_HDMI_POL(0xf))
+#define M_RK3399_DSP_LVDS_POL          (V_RK3399_DSP_LVDS_POL(0xf))
+
 #define M_DSP_LAYER3_SEL               (3 << 14)
 #define M_DSP_LAYER2_SEL               (3 << 12)
 #define M_DSP_LAYER1_SEL               (3 << 10)