diff options
| author | Vikas Manocha <vikas.manocha@st.com> | 2014-11-18 10:42:23 -0800 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-12-09 15:16:19 -0500 |
| commit | 2ce4eaf4c89e371aeb69392b68dbb2f705c28144 (patch) | |
| tree | 56c27ac25726f80f1bf7844222f8fadea3cdec8a /arch/arm/include/asm/arch-stv0991/stv0991_cgu.h | |
| parent | 9fa32b12370236a39090d4e42b013910d123db61 (diff) | |
stv0991: enable ethernet support
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Diffstat (limited to 'arch/arm/include/asm/arch-stv0991/stv0991_cgu.h')
| -rw-r--r-- | arch/arm/include/asm/arch-stv0991/stv0991_cgu.h | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h b/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h index 4926395622..ddcbb57a92 100644 --- a/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h +++ b/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h @@ -77,4 +77,40 @@ struct stv0991_cgu_regs { #define UART_CLK_CFG (4 << DIV_SHIFT_UART \ | 1 << MDIV_SHIFT_UART | CLK_UART_MCLK) +/* CGU Ethernet clock config */ +#define CLK_ETH_MCLK 0 +#define CLK_ETH_PLL1 1 +#define CLK_ETH_PLL2 2 + +#define MDIV_SHIFT_ETH 3 +#define DIV_SHIFT_ETH 6 +#define DIV_ETH_125 9 +#define DIV_ETH_50 12 +#define DIV_ETH_P2P 15 + +#define ETH_CLK_CFG (4 << DIV_ETH_P2P | 4 << DIV_ETH_50 \ + | 1 << DIV_ETH_125 \ + | 0 << DIV_SHIFT_ETH \ + | 3 << MDIV_SHIFT_ETH | CLK_ETH_PLL1) + /* CGU Ethernet control */ + +#define ETH_CLK_TX_EXT_PHY 0 +#define ETH_CLK_TX_125M 1 +#define ETH_CLK_TX_25M 2 +#define ETH_CLK_TX_2M5 3 +#define ETH_CLK_TX_DIS 7 + +#define ETH_CLK_RX_EXT_PHY 0 +#define ETH_CLK_RX_25M 1 +#define ETH_CLK_RX_2M5 2 +#define ETH_CLK_RX_DIS 3 +#define RX_CLK_SHIFT 3 +#define ETH_CLK_MASK ~(0x1F) + +#define ETH_PHY_MODE_GMII 0 +#define ETH_PHY_MODE_RMII 1 +#define ETH_PHY_CLK_DIS 1 + +#define ETH_CLK_CTRL (ETH_CLK_RX_EXT_PHY << RX_CLK_SHIFT \ + | ETH_CLK_TX_EXT_PHY) #endif |