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authorIcenowy Zheng <icenowy@aosc.io>2017-05-01 14:31:56 +0800
committerMaxime Ripard <maxime.ripard@free-electrons.com>2017-05-02 09:21:09 +0200
commit9946631a0f2d8e8493ea17e9fe1f0e190aa3372d (patch)
tree886fbc45128cae2a2ea7d6bfd1e4c63524d6a5d9 /arch/arm/include/asm/arch-sunxi
parentaf83a604b33dde3bbc75fe7b467e649970d674e8 (diff)
sunxi: add clock configuration of R40 sata
R40 has a similar SATA controller with the ones on A10/A20, but with a reset line added (like other peripherals on sun6i+), and two extra VDD pins added (1.2v and 2.5v). Add clock configuration of R40 SATA. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'arch/arm/include/asm/arch-sunxi')
-rw-r--r--arch/arm/include/asm/arch-sunxi/clock_sun6i.h18
1 files changed, 16 insertions, 2 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index a44ea77576..faa14791f9 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -25,7 +25,7 @@ struct sunxi_ccm_reg {
u32 pll6_cfg; /* 0x28 pll6 control */
u32 reserved5;
u32 pll7_cfg; /* 0x30 pll7 control */
- u32 reserved6;
+ u32 sata_pll_cfg; /* 0x34 SATA pll control (R40 only) */
u32 pll8_cfg; /* 0x38 pll8 control */
u32 reserved7;
u32 mipi_pll_cfg; /* 0x40 MIPI pll control */
@@ -58,7 +58,8 @@ struct sunxi_ccm_reg {
u32 i2s1_clk_cfg; /* 0xb4 I2S1 clock control */
u32 reserved10[2];
u32 spdif_clk_cfg; /* 0xc0 SPDIF clock control */
- u32 reserved11[2];
+ u32 reserved11;
+ u32 sata_clk_cfg; /* 0xc8 SATA clock control (R40 only) */
u32 usb_clk_cfg; /* 0xcc USB clock control */
u32 gmac_clk_cfg; /* 0xd0 GMAC clock control */
u32 reserved12[7];
@@ -224,6 +225,8 @@ struct sunxi_ccm_reg {
#define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT)
#define CCM_PLL6_CTRL_LOCK (1 << 28)
+#define CCM_SATA_PLL_DEFAULT 0x90005811 /* 100 MHz */
+
#define CCM_MIPI_PLL_CTRL_M_SHIFT 0
#define CCM_MIPI_PLL_CTRL_M_MASK (0xf << CCM_MIPI_PLL_CTRL_M_SHIFT)
#define CCM_MIPI_PLL_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
@@ -280,7 +283,12 @@ struct sunxi_ccm_reg {
#define AHB_GATE_OFFSET_USB_EHCI1 27
#define AHB_GATE_OFFSET_USB_EHCI0 26
#endif
+#ifndef CONFIG_MACH_SUN8I_R40
#define AHB_GATE_OFFSET_USB0 24
+#else
+#define AHB_GATE_OFFSET_USB0 25
+#define AHB_GATE_OFFSET_SATA 24
+#endif
#define AHB_GATE_OFFSET_MCTL 14
#define AHB_GATE_OFFSET_GMAC 17
#define AHB_GATE_OFFSET_NAND0 13
@@ -315,6 +323,9 @@ struct sunxi_ccm_reg {
#define CCM_MMC_CTRL_PLL6 (0x1 << 24)
#define CCM_MMC_CTRL_ENABLE (0x1 << 31)
+#define CCM_SATA_CTRL_ENABLE (0x1 << 31)
+#define CCM_SATA_CTRL_USE_EXTCLK (0x1 << 24)
+
#define CCM_USB_CTRL_PHY0_RST (0x1 << 0)
#define CCM_USB_CTRL_PHY1_RST (0x1 << 1)
#define CCM_USB_CTRL_PHY2_RST (0x1 << 2)
@@ -417,6 +428,9 @@ struct sunxi_ccm_reg {
#define CCM_PLL11_PATTERN 0xf5860000
/* ahb_reset0 offsets */
+#ifdef CONFIG_MACH_SUN8I_R40
+#define AHB_RESET_OFFSET_SATA 24
+#endif
#define AHB_RESET_OFFSET_GMAC 17
#define AHB_RESET_OFFSET_MCTL 14
#define AHB_RESET_OFFSET_MMC3 11