diff options
| author | Thierry Reding <treding@nvidia.com> | 2015-08-20 11:42:19 +0200 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2015-09-16 16:10:22 -0700 |
| commit | c043c0259cd88f39cdca5f98af8b10f178660745 (patch) | |
| tree | 6def8ed72abc3fb8155956a6dff7f9c24fae3952 /arch/arm/include/asm/arch-tegra/clock.h | |
| parent | 70bcb43e7d943f5f437e84594e0b890b0869be23 (diff) | |
ARM: tegra: Implement clk_m
On currently supported SoCs, clk_m always runs at the same frequency as
the oscillator input. However newer SoC generations such as Tegra210 no
longer have that restriction. Prepare for that by separating clk_m from
the oscillator clock and allow SoC code to override the clk_m rate.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/include/asm/arch-tegra/clock.h')
| -rw-r--r-- | arch/arm/include/asm/arch-tegra/clock.h | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h index d570d7f134..e56031d1af 100644 --- a/arch/arm/include/asm/arch-tegra/clock.h +++ b/arch/arm/include/asm/arch-tegra/clock.h @@ -44,6 +44,9 @@ enum { /* return the current oscillator clock frequency */ enum clock_osc_freq clock_get_osc_freq(void); +/* return the clk_m frequency */ +unsigned int clk_m_get_rate(unsigned int parent_rate); + /** * Start PLL using the provided configuration parameters. * @@ -338,8 +341,8 @@ void arch_timer_init(void); void tegra30_set_up_pllp(void); -/* Number of PLL-based clocks (i.e. not OSC or 32KHz) */ -#define CLOCK_ID_PLL_COUNT (CLOCK_ID_COUNT - 2) +/* Number of PLL-based clocks (i.e. not OSC, MCLK or 32KHz) */ +#define CLOCK_ID_PLL_COUNT (CLOCK_ID_COUNT - 3) struct clk_pll_info { u32 m_shift:5; /* DIVM_SHIFT */ |