diff options
| author | Stephen Warren <swarren@nvidia.com> | 2018-06-22 13:02:27 -0600 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2018-07-26 13:15:29 -0700 |
| commit | daebd48fe849552ce9de9d6311f525134b138974 (patch) | |
| tree | 196d663dc4fd9712c5804c6b0b13dac84c9ab3af /arch/arm/include/asm/arch-tegra124 | |
| parent | 2547e91dc15e5203e15d4ebde9172174743b14a7 (diff) | |
Revert "tegra: Introduce SRAM repair on tegra124"
This reverts commit 701b7b1d2cf657d435d2bd6caf43d0247d37220d. It will
be immediately replaced by a different implementation that is more
complete and runs are more targetted times.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/include/asm/arch-tegra124')
| -rw-r--r-- | arch/arm/include/asm/arch-tegra124/flow.h | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/arch/arm/include/asm/arch-tegra124/flow.h b/arch/arm/include/asm/arch-tegra124/flow.h index a54425692b..2b330dc9e1 100644 --- a/arch/arm/include/asm/arch-tegra124/flow.h +++ b/arch/arm/include/asm/arch-tegra124/flow.h @@ -25,12 +25,6 @@ struct flow_ctlr { u32 cpu_pwr_csr; /* offset 0x38 */ u32 mpid; /* offset 0x3c */ u32 ram_repair; /* offset 0x40 */ - u32 flow_dbg_sel; /* offset 0x44 */ - u32 flow_dbg_cnt0; /* offset 0x48 */ - u32 flow_dbg_cnt1; /* offset 0x4c */ - u32 flow_dbg_qual; /* offset 0x50 */ - u32 flow_ctlr_spare; /* offset 0x54 */ - u32 ram_repair_cluster1;/* offset 0x58 */ }; /* HALT_COP_EVENTS_0, 0x04 */ @@ -48,10 +42,4 @@ struct flow_ctlr { #define CSR_WAIT_WFI_SHIFT 8 #define CSR_PWR_OFF_STS (1 << 16) -/* RAM_REPAIR, 0x40, 0x58 */ -enum { - RAM_REPAIR_REQ = 0x1 << 0, - RAM_REPAIR_STS = 0x1 << 1, -}; - #endif /* _TEGRA124_FLOW_H_ */ |