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authorSimon Glass <sjg@chromium.org>2012-04-02 13:18:50 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-05-15 08:31:37 +0200
commitd515362d4d6f83be818f71d37a4600041a520ab5 (patch)
tree30b7c1e6fc2c319377369ba1eebf815fead3dcb3 /arch/arm/include/asm/arch-tegra2/tegra2.h
parentf6f767a4040110b400726e9859ea51a7ade10474 (diff)
tegra: Add tegra_get_chip_type() to detect SKU
We want to know which type of chip we are running on - the Tegra family has several SKUs. This can be determined by reading a fuse register, so add this function to ap20. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/include/asm/arch-tegra2/tegra2.h')
-rw-r--r--arch/arm/include/asm/arch-tegra2/tegra2.h24
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-tegra2/tegra2.h b/arch/arm/include/asm/arch-tegra2/tegra2.h
index 2e152fd077..d4ada10ea8 100644
--- a/arch/arm/include/asm/arch-tegra2/tegra2.h
+++ b/arch/arm/include/asm/arch-tegra2/tegra2.h
@@ -33,6 +33,7 @@
#define NV_PA_GPIO_BASE 0x6000D000
#define NV_PA_EVP_BASE 0x6000F000
#define NV_PA_APB_MISC_BASE 0x70000000
+#define TEGRA2_APB_MISC_GP_BASE (NV_PA_APB_MISC_BASE + 0x0800)
#define NV_PA_APB_UARTA_BASE (NV_PA_APB_MISC_BASE + 0x6000)
#define NV_PA_APB_UARTB_BASE (NV_PA_APB_MISC_BASE + 0x6040)
#define NV_PA_APB_UARTC_BASE (NV_PA_APB_MISC_BASE + 0x6200)
@@ -55,6 +56,29 @@
struct timerus {
unsigned int cntr_1us;
};
+
+/* Address at which WB code runs, it must not overlap Bootrom's IRAM usage */
+#define AP20_WB_RUN_ADDRESS 0x40020000
+
+/* These are the available SKUs (product types) for Tegra */
+enum {
+ SKU_ID_T20 = 0x8,
+ SKU_ID_T25SE = 0x14,
+ SKU_ID_AP25 = 0x17,
+ SKU_ID_T25 = 0x18,
+ SKU_ID_AP25E = 0x1b,
+ SKU_ID_T25E = 0x1c,
+};
+
+/* These are the SOC categories that affect clocking */
+enum {
+ TEGRA_SOC_T20,
+ TEGRA_SOC_T25,
+
+ TEGRA_SOC_COUNT,
+ TEGRA_SOC_UNKNOWN = -1,
+};
+
#else /* __ASSEMBLY__ */
#define PRM_RSTCTRL TEGRA2_PMC_BASE
#endif