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author | Icenowy Zheng <icenowy@aosc.xyz> | 2017-06-03 17:10:16 +0800 |
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committer | Jagan Teki <jagan@amarulasolutions.com> | 2017-06-08 22:37:55 +0530 |
commit | 87098d701da77f264c9cbed67a5d6fb27fbaaf3f (patch) | |
tree | d4321481b59e6f2969efd57b810f91737c28c4a5 /arch/arm/include/asm/arch-tegra30 | |
parent | f43a009959e6c1f1ace8b76ef525651ac4729c9d (diff) |
sunxi: add option for 16-bit DW DRAM controller
Some Allwinner SoCs features a DesignWare-like controller with only 16
bit bus width.
Add support for them.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
Diffstat (limited to 'arch/arm/include/asm/arch-tegra30')
0 files changed, 0 insertions, 0 deletions