diff options
| author | Stefan Agner <stefan@agner.ch> | 2014-08-06 10:59:36 +0200 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-08-30 07:46:40 -0400 |
| commit | b0e31c7b66314ccc64ce51fb1b3032946a5f74e3 (patch) | |
| tree | c71a79839a83de309363b6296320902e98beb6c3 /arch/arm/include/asm/arch-vf610/crm_regs.h | |
| parent | baa3134440fab74b0048c9cbb42b7e86f4687309 (diff) | |
arm: vf610: add NFC clock support
Add NFC (NAND Flash Controller) clock support and enable them
at board initialization time.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Diffstat (limited to 'arch/arm/include/asm/arch-vf610/crm_regs.h')
| -rw-r--r-- | arch/arm/include/asm/arch-vf610/crm_regs.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h index 5256624adf..724682c683 100644 --- a/arch/arm/include/asm/arch-vf610/crm_regs.h +++ b/arch/arm/include/asm/arch-vf610/crm_regs.h @@ -156,14 +156,27 @@ struct anadig_reg { #define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET 18 #define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 18) #define CCM_CSCMR1_ESDHC1_CLK_SEL(v) (((v) & 0x3) << 18) +#define CCM_CSCMR1_NFC_CLK_SEL_OFFSET 12 +#define CCM_CSCMR1_NFC_CLK_SEL_MASK (0x3 << 12) +#define CCM_CSCMR1_NFC_CLK_SEL(v) (((v) & 0x3) << 12) #define CCM_CSCDR1_RMII_CLK_EN (1 << 24) +#define CCM_CSCDR2_NFC_EN (1 << 9) +#define CCM_CSCDR2_NFC_FRAC_DIV_EN (1 << 13) +#define CCM_CSCDR2_NFC_CLK_INV (1 << 14) +#define CCM_CSCDR2_NFC_FRAC_DIV_OFFSET 4 +#define CCM_CSCDR2_NFC_FRAC_DIV_MASK (0xf << 4) +#define CCM_CSCDR2_NFC_FRAC_DIV(v) (((v) & 0xf) << 4) + #define CCM_CSCDR2_ESDHC1_EN (1 << 29) #define CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET 20 #define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK (0xf << 20) #define CCM_CSCDR2_ESDHC1_CLK_DIV(v) (((v) & 0xf) << 20) +#define CCM_CSCDR3_NFC_PRE_DIV_OFFSET 13 +#define CCM_CSCDR3_NFC_PRE_DIV_MASK (0x7 << 13) +#define CCM_CSCDR3_NFC_PRE_DIV(v) (((v) & 0x7) << 13) #define CCM_CSCDR3_QSPI0_EN (1 << 4) #define CCM_CSCDR3_QSPI0_DIV(v) ((v) << 3) #define CCM_CSCDR3_QSPI0_X2_DIV(v) ((v) << 2) @@ -195,6 +208,7 @@ struct anadig_reg { #define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 << 4) #define CCM_CCGR9_FEC0_CTRL_MASK 0x3 #define CCM_CCGR9_FEC1_CTRL_MASK (0x3 << 2) +#define CCM_CCGR10_NFC_CTRL_MASK 0x3 #define ANADIG_PLL5_CTRL_BYPASS (1 << 16) #define ANADIG_PLL5_CTRL_ENABLE (1 << 13) |