arm64: zynqmp: Move SoC sources to mach-zynqmp

Similar changes was done for Zynq in past and this patch just follow
this pattern to separate cpu code from SoC code.

Move arch/arm/cpu/armv8/zynqmp/* -> arch/arm/mach-zynqmp/*
And also fix references to these files.

Based on
"ARM: zynq: move SoC sources to mach-zynq"
(sha1: 0107f2403669f764ab726d0d404e35bb9447bbcc)

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

5 files changed, 0 insertions, 282 deletions

diff --git a/arch/arm/include/asm/arch-zynqmp/clk.h b/arch/arm/include/asm/arch-zynqmp/clk.h
deleted file mode 100644
index cfd44c8e0f..0000000000
--- a/arch/arm/include/asm/arch-zynqmp/clk.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2014 - 2015 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
- */
-
-#ifndef _ASM_ARCH_CLK_H_
-#define _ASM_ARCH_CLK_H_
-
-unsigned long zynqmp_get_system_timer_freq(void);
-
-#endif /* _ASM_ARCH_CLK_H_ */
diff --git a/arch/arm/include/asm/arch-zynqmp/gpio.h b/arch/arm/include/asm/arch-zynqmp/gpio.h
deleted file mode 100644
index 542a5fc3e9..0000000000
--- a/arch/arm/include/asm/arch-zynqmp/gpio.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2015 Xilinx, Inc.
- */
-
-#ifndef __ARCH_ZYNQMP_GPIO_H
-#define __ARCH_ZYNQMP_GPIO_H
-
-/* Empty file - sdhci requires this. */
-
-#endif
diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h
deleted file mode 100644
index 8a505edab3..0000000000
--- a/arch/arm/include/asm/arch-zynqmp/hardware.h
+++ /dev/null
@@ -1,159 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2014 - 2015 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
- */
-
-#ifndef _ASM_ARCH_HARDWARE_H
-#define _ASM_ARCH_HARDWARE_H
-
-#define ZYNQ_GEM_BASEADDR0	0xFF0B0000
-#define ZYNQ_GEM_BASEADDR1	0xFF0C0000
-#define ZYNQ_GEM_BASEADDR2	0xFF0D0000
-#define ZYNQ_GEM_BASEADDR3	0xFF0E0000
-
-#define ZYNQ_I2C_BASEADDR0	0xFF020000
-#define ZYNQ_I2C_BASEADDR1	0xFF030000
-
-#define ARASAN_NAND_BASEADDR	0xFF100000
-
-#define ZYNQMP_TCM_BASE_ADDR	0xFFE00000
-#define ZYNQMP_TCM_SIZE		0x40000
-
-#define ZYNQMP_CRL_APB_BASEADDR	0xFF5E0000
-#define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT	0x1000000
-#define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT	0
-#define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT	8
-
-#define PS_MODE0	BIT(0)
-#define PS_MODE1	BIT(1)
-#define PS_MODE2	BIT(2)
-#define PS_MODE3	BIT(3)
-
-#define RESET_REASON_DEBUG_SYS	BIT(6)
-#define RESET_REASON_SOFT	BIT(5)
-#define RESET_REASON_SRST	BIT(4)
-#define RESET_REASON_PSONLY	BIT(3)
-#define RESET_REASON_PMU	BIT(2)
-#define RESET_REASON_INTERNAL	BIT(1)
-#define RESET_REASON_EXTERNAL	BIT(0)
-
-struct crlapb_regs {
-	u32 reserved0[36];
-	u32 cpu_r5_ctrl; /* 0x90 */
-	u32 reserved1[37];
-	u32 timestamp_ref_ctrl; /* 0x128 */
-	u32 reserved2[53];
-	u32 boot_mode; /* 0x200 */
-	u32 reserved3_0[7];
-	u32 reset_reason; /* 0x220 */
-	u32 reserved3_1[6];
-	u32 rst_lpd_top; /* 0x23C */
-	u32 reserved4[4];
-	u32 boot_pin_ctrl; /* 0x250 */
-	u32 reserved5[21];
-};
-
-#define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR)
-
-#define ZYNQMP_IOU_SCNTR_SECURE	0xFF260000
-#define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN	0x1
-#define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG	0x2
-
-struct iou_scntr_secure {
-	u32 counter_control_register;
-	u32 reserved0[7];
-	u32 base_frequency_id_register;
-};
-
-#define iou_scntr_secure ((struct iou_scntr_secure *)ZYNQMP_IOU_SCNTR_SECURE)
-
-/* Bootmode setting values */
-#define BOOT_MODES_MASK	0x0000000F
-#define QSPI_MODE_24BIT	0x00000001
-#define QSPI_MODE_32BIT	0x00000002
-#define SD_MODE		0x00000003 /* sd 0 */
-#define SD_MODE1	0x00000005 /* sd 1 */
-#define NAND_MODE	0x00000004
-#define EMMC_MODE	0x00000006
-#define USB_MODE	0x00000007
-#define SD1_LSHFT_MODE	0x0000000E /* SD1 Level shifter */
-#define JTAG_MODE	0x00000000
-#define BOOT_MODE_USE_ALT	0x100
-#define BOOT_MODE_ALT_SHIFT	12
-/* SW secondary boot modes 0xa - 0xd */
-#define SW_USBHOST_MODE	0x0000000A
-#define SW_SATA_MODE	0x0000000B
-
-#define ZYNQMP_IOU_SLCR_BASEADDR	0xFF180000
-
-struct iou_slcr_regs {
-	u32 mio_pin[78];
-	u32 reserved[442];
-};
-
-#define slcr_base ((struct iou_slcr_regs *)ZYNQMP_IOU_SLCR_BASEADDR)
-
-#define ZYNQMP_RPU_BASEADDR	0xFF9A0000
-
-struct rpu_regs {
-	u32 rpu_glbl_ctrl;
-	u32 reserved0[63];
-	u32 rpu0_cfg; /* 0x100 */
-	u32 reserved1[63];
-	u32 rpu1_cfg; /* 0x200 */
-};
-
-#define rpu_base ((struct rpu_regs *)ZYNQMP_RPU_BASEADDR)
-
-#define ZYNQMP_CRF_APB_BASEADDR	0xFD1A0000
-
-struct crfapb_regs {
-	u32 reserved0[65];
-	u32 rst_fpd_apu; /* 0x104 */
-	u32 reserved1;
-};
-
-#define crfapb_base ((struct crfapb_regs *)ZYNQMP_CRF_APB_BASEADDR)
-
-#define ZYNQMP_APU_BASEADDR	0xFD5C0000
-
-struct apu_regs {
-	u32 reserved0[16];
-	u32 rvbar_addr0_l; /* 0x40 */
-	u32 rvbar_addr0_h; /* 0x44 */
-	u32 reserved1[20];
-};
-
-#define apu_base ((struct apu_regs *)ZYNQMP_APU_BASEADDR)
-
-/* Board version value */
-#define ZYNQMP_CSU_BASEADDR		0xFFCA0000
-#define ZYNQMP_CSU_VERSION_SILICON	0x0
-#define ZYNQMP_CSU_VERSION_QEMU		0x3
-
-#define ZYNQMP_CSU_VERSION_EMPTY_SHIFT		20
-
-#define ZYNQMP_SILICON_VER_MASK		0xF000
-#define ZYNQMP_SILICON_VER_SHIFT	12
-
-struct csu_regs {
-	u32 reserved0[17];
-	u32 version;
-};
-
-#define csu_base ((struct csu_regs *)ZYNQMP_CSU_BASEADDR)
-
-#define ZYNQMP_PMU_BASEADDR	0xFFD80000
-
-struct pmu_regs {
-	u32 reserved[18];
-	u32 gen_storage6; /* 0x48 */
-};
-
-#define pmu_base ((struct pmu_regs *)ZYNQMP_PMU_BASEADDR)
-
-#define ZYNQMP_CSU_IDCODE_ADDR	0xFFCA0040
-#define ZYNQMP_CSU_VER_ADDR	0xFFCA0044
-
-#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-zynqmp/psu_init_gpl.h b/arch/arm/include/asm/arch-zynqmp/psu_init_gpl.h
deleted file mode 100644
index 15e54c0493..0000000000
--- a/arch/arm/include/asm/arch-zynqmp/psu_init_gpl.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-
-#ifndef _PSU_INIT_GPL_H_ /* prevent circular inclusions */
-#define _PSU_INIT_GPL_H_
-
-#include <asm/io.h>
-#include <common.h>
-
-int mask_pollonvalue(unsigned long add, u32 mask, u32 value);
-
-int mask_poll(u32 add, u32 mask);
-
-u32 mask_read(u32 add, u32 mask);
-
-void mask_delay(u32 delay);
-
-void psu_mask_write(unsigned long offset, unsigned long mask,
-		    unsigned long val);
-
-void prog_reg(unsigned long addr, unsigned long mask,
-	      unsigned long shift, unsigned long value);
-
-int psu_init(void);
-
-#endif /* _PSU_INIT_GPL_H_ */
diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h
deleted file mode 100644
index 385c8825f2..0000000000
--- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2014 - 2015 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
- */
-
-#ifndef _ASM_ARCH_SYS_PROTO_H
-#define _ASM_ARCH_SYS_PROTO_H
-
-#define PAYLOAD_ARG_CNT		5
-
-#define ZYNQMP_CSU_SILICON_VER_MASK	0xF
-#define ZYNQMP_SIP_SVC_PM_SECURE_IMG_LOAD	0xC200002D
-#define KEY_PTR_LEN	32
-
-#define ZYNQMP_FPGA_BIT_AUTH_DDR	1
-#define ZYNQMP_FPGA_BIT_AUTH_OCM	2
-#define ZYNQMP_FPGA_BIT_ENC_USR_KEY	3
-#define ZYNQMP_FPGA_BIT_ENC_DEV_KEY	4
-#define ZYNQMP_FPGA_BIT_NS		5
-
-#define ZYNQMP_FPGA_AUTH_DDR	1
-
-#define ZYNQMP_SIP_SVC_GET_API_VERSION		0xC2000001
-
-#define ZYNQMP_PM_VERSION_MAJOR		1
-#define ZYNQMP_PM_VERSION_MINOR		0
-#define ZYNQMP_PM_VERSION_MAJOR_SHIFT	16
-#define ZYNQMP_PM_VERSION_MINOR_MASK	0xFFFF
-
-#define ZYNQMP_PM_VERSION	\
-	((ZYNQMP_PM_VERSION_MAJOR << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | \
-				 ZYNQMP_PM_VERSION_MINOR)
-
-#define ZYNQMP_PM_VERSION_INVALID	~0
-
-#define PMUFW_V1_0	((1 << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | 0)
-
-enum {
-	IDCODE,
-	VERSION,
-	IDCODE2,
-};
-
-enum {
-	ZYNQMP_SILICON_V1,
-	ZYNQMP_SILICON_V2,
-	ZYNQMP_SILICON_V3,
-	ZYNQMP_SILICON_V4,
-};
-
-enum {
-	TCM_LOCK,
-	TCM_SPLIT,
-};
-
-int zynq_board_read_rom_ethaddr(unsigned char *ethaddr);
-unsigned int zynqmp_get_silicon_version(void);
-
-void handoff_setup(void);
-
-unsigned int zynqmp_pmufw_version(void);
-int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
-int zynqmp_mmio_read(const u32 address, u32 *value);
-int invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3,
-	       u32 *ret_payload);
-
-void initialize_tcm(bool mode);
-void mem_map_fill(void);
-int chip_id(unsigned char id);
-#if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP)
-void tcm_init(u8 mode);
-#endif
-
-#endif /* _ASM_ARCH_SYS_PROTO_H */