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| author | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2013-03-28 18:50:01 +0100 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2013-03-28 18:50:01 +0100 |
| commit | 009d75ccc11d27b9a083375a88bb93cb746b4800 (patch) | |
| tree | 12abe9fcf437d58b73ee1fa8d422548560deaae5 /arch/arm/include/asm/cache.h | |
| parent | 417c55803118eb8e350d5ab8ba6583fb39f4e2e3 (diff) | |
| parent | d53e340edf65ff253d3a7b06ebe60501045892e3 (diff) | |
Merge branch 'u-boot/master' into 'u-boot-arm/master'
Conflicts:
drivers/spi/tegra20_sflash.c
include/fdtdec.h
lib/fdtdec.c
Diffstat (limited to 'arch/arm/include/asm/cache.h')
| -rw-r--r-- | arch/arm/include/asm/cache.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index eef6a5a8f2..8153484899 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -41,7 +41,9 @@ static inline void invalidate_l2_cache(void) void l2_cache_enable(void); void l2_cache_disable(void); +void set_section_dcache(int section, enum dcache_option option); +void dram_bank_mmu_setup(int bank); /* * The current upper bound for ARM L1 data cache line sizes is 64 bytes. We * use that value for aligning DMA buffers unless the board config has specified |