diff options
| author | Lokesh Vutla <lokeshvutla@ti.com> | 2012-05-22 00:03:24 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-07-07 14:07:23 +0200 |
| commit | 43037d76316db1a53be16a4c1ed97203257fa4ee (patch) | |
| tree | c549887069235d35144830a8ec0bcf9346c1d1ca /arch/arm/include/asm/emif.h | |
| parent | eb4e18e89eec8d63f064cb5ec597ba9387fe4987 (diff) | |
OMAP5: ADD precalculated timings for ddr3
Adding precalculated timings for ddr3 with 1cs
adding required registers for ddr3
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch/arm/include/asm/emif.h')
| -rw-r--r-- | arch/arm/include/asm/emif.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index f1e3ad212e..5d2649e121 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -650,6 +650,7 @@ struct dmm_lisa_map_regs { }; extern const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG]; +extern const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG]; #define CS0 0 #define CS1 1 @@ -1073,6 +1074,10 @@ struct emif_regs { u32 emif_ddr_ext_phy_ctrl_3; u32 emif_ddr_ext_phy_ctrl_4; u32 emif_ddr_ext_phy_ctrl_5; + u32 emif_rd_wr_lvl_rmp_win; + u32 emif_rd_wr_lvl_rmp_ctl; + u32 emif_rd_wr_lvl_ctl; + u32 emif_rd_wr_exec_thresh; }; /* assert macros */ |