diff options
| author | Sumit Garg <sumit.garg@nxp.com> | 2017-08-16 07:13:28 -0400 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2017-09-11 07:55:36 -0700 |
| commit | 06fb06f66c57912b53bda9fd1772d5d069433cbd (patch) | |
| tree | f46c4f8ad8eac2fd6958627011212bb2ab423085 /arch/arm/include/asm/fsl_secure_boot.h | |
| parent | a7a81756b8851b84de11c8e755b2e63d907336d4 (diff) | |
SECURE_BOOT: Unify memory map for Layerscape based platforms
Unify memory map for Layerscape based platforms. This patch includes
changes in bootscript, bootscript header and PPA header addresses
change as per unified memory map.
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Tested-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/include/asm/fsl_secure_boot.h')
| -rw-r--r-- | arch/arm/include/asm/fsl_secure_boot.h | 54 |
1 files changed, 22 insertions, 32 deletions
diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index b0b3b9377e..63845a2460 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -1,5 +1,6 @@ /* * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -71,55 +72,44 @@ * DDR memory map */ #ifdef CONFIG_FSL_LSCH3 -#define CONFIG_BS_HDR_ADDR_DEVICE 0x580d00000 -#define CONFIG_BS_ADDR_DEVICE 0x580e00000 -#define CONFIG_BS_HDR_ADDR_RAM 0xa0d00000 -#define CONFIG_BS_ADDR_RAM 0xa0e00000 -#define CONFIG_BS_HDR_SIZE 0x00002000 +#define CONFIG_BS_ADDR_DEVICE 0x580600000 +#define CONFIG_BS_HDR_ADDR_DEVICE 0x580640000 #define CONFIG_BS_SIZE 0x00001000 +#define CONFIG_BS_HDR_SIZE 0x00004000 +#define CONFIG_BS_ADDR_RAM 0xa0600000 +#define CONFIG_BS_HDR_ADDR_RAM 0xa0640000 #else #ifdef CONFIG_SD_BOOT /* For SD boot address and size are assigned in terms of sector * offset and no. of sectors respectively. */ -#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) -#define CONFIG_BS_HDR_ADDR_DEVICE 0x00000920 -#else -#define CONFIG_BS_HDR_ADDR_DEVICE 0x00000900 -#endif -#define CONFIG_BS_ADDR_DEVICE 0x00000940 -#define CONFIG_BS_HDR_SIZE 0x00000010 +#define CONFIG_BS_ADDR_DEVICE 0x00003000 +#define CONFIG_BS_HDR_ADDR_DEVICE 0x00003200 #define CONFIG_BS_SIZE 0x00000008 +#define CONFIG_BS_HDR_SIZE 0x00000010 #elif defined(CONFIG_NAND_BOOT) -#define CONFIG_BS_HDR_ADDR_DEVICE 0x00800000 -#define CONFIG_BS_ADDR_DEVICE 0x00802000 -#define CONFIG_BS_HDR_SIZE 0x00002000 -#define CONFIG_BS_SIZE 0x00001000 -#elif defined(CONFIG_QSPI_BOOT) -#ifdef CONFIG_ARCH_LS1046A -#define CONFIG_BS_HDR_ADDR_DEVICE 0x40780000 -#define CONFIG_BS_ADDR_DEVICE 0x40800000 -#elif defined(CONFIG_ARCH_LS1012A) -#define CONFIG_BS_HDR_ADDR_DEVICE 0x400c0000 -#define CONFIG_BS_ADDR_DEVICE 0x40060000 -#else -#error "Platform not supported" -#endif +#define CONFIG_BS_ADDR_DEVICE 0x00600000 +#define CONFIG_BS_HDR_ADDR_DEVICE 0x00640000 +#define CONFIG_BS_SIZE 0x00001000 #define CONFIG_BS_HDR_SIZE 0x00002000 +#elif defined(CONFIG_QSPI_BOOT) +#define CONFIG_BS_ADDR_DEVICE 0x40600000 +#define CONFIG_BS_HDR_ADDR_DEVICE 0x40640000 #define CONFIG_BS_SIZE 0x00001000 -#else /* Default NOR Boot */ -#define CONFIG_BS_HDR_ADDR_DEVICE 0x600a0000 -#define CONFIG_BS_ADDR_DEVICE 0x60060000 #define CONFIG_BS_HDR_SIZE 0x00002000 +#else /* Default NOR Boot */ +#define CONFIG_BS_ADDR_DEVICE 0x60600000 +#define CONFIG_BS_HDR_ADDR_DEVICE 0x60640000 #define CONFIG_BS_SIZE 0x00001000 +#define CONFIG_BS_HDR_SIZE 0x00002000 #endif -#define CONFIG_BS_HDR_ADDR_RAM 0x81000000 -#define CONFIG_BS_ADDR_RAM 0x81020000 +#define CONFIG_BS_ADDR_RAM 0x81000000 +#define CONFIG_BS_HDR_ADDR_RAM 0x81020000 #endif #ifdef CONFIG_BOOTSCRIPT_COPY_RAM -#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM #define CONFIG_BOOTSCRIPT_ADDR CONFIG_BS_ADDR_RAM +#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM #else #define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_DEVICE /* BOOTSCRIPT_ADDR is not required */ |