diff options
| author | Scott Branden <sbranden@broadcom.com> | 2014-08-11 13:58:22 -0700 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-08-30 07:46:40 -0400 |
| commit | c4b4500910b2dac1dd2e02fb498c059688fb606a (patch) | |
| tree | 6bf8e922455f18eb3f8dbdaaf205aa9b04c38db5 /arch/arm/include/asm/iproc-common/sysmap.h | |
| parent | b0e31c7b66314ccc64ce51fb1b3032946a5f74e3 (diff) | |
arm: iproc: Initial commit of iproc architecture code
The iproc architecture code is present in several Broadcom
chip architectures, including Cygnus and NSP.
Signed-off-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
Diffstat (limited to 'arch/arm/include/asm/iproc-common/sysmap.h')
| -rw-r--r-- | arch/arm/include/asm/iproc-common/sysmap.h | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/arch/arm/include/asm/iproc-common/sysmap.h b/arch/arm/include/asm/iproc-common/sysmap.h new file mode 100644 index 0000000000..5766dc9e53 --- /dev/null +++ b/arch/arm/include/asm/iproc-common/sysmap.h @@ -0,0 +1,47 @@ +/* + * Copyright 2014 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SYSMAP_H +#define __SYSMAP_H + +#define IHOST_PROC_CLK_PLLARMA 0X19000C00 +#define IHOST_PROC_CLK_PLLARMB 0X19000C04 +#define IHOST_PROC_CLK_PLLARMA__PLLARM_PDIV_R 24 + +#define IHOST_PROC_CLK_WR_ACCESS 0X19000000 +#define IHOST_PROC_CLK_POLICY_FREQ 0X19000008 +#define IHOST_PROC_CLK_POLICY_FREQ__PRIV_ACCESS_MODE 31 +#define IHOST_PROC_CLK_POLICY_FREQ__POLICY3_FREQ_R 24 +#define IHOST_PROC_CLK_POLICY_FREQ__POLICY2_FREQ_R 16 +#define IHOST_PROC_CLK_POLICY_FREQ__POLICY1_FREQ_R 8 +#define IHOST_PROC_CLK_POLICY_CTL 0X1900000C +#define IHOST_PROC_CLK_POLICY_CTL__GO 0 +#define IHOST_PROC_CLK_POLICY_CTL__GO_AC 1 +#define IHOST_PROC_CLK_PLLARMB__PLLARM_NDIV_FRAC_R 0 +#define IHOST_PROC_CLK_PLLARMB__PLLARM_NDIV_FRAC_WIDTH 20 +#define IHOST_PROC_CLK_PLLARMA__PLLARM_LOCK 28 +#define IHOST_PROC_CLK_POLICY_FREQ__POLICY0_FREQ_R 0 +#define IHOST_PROC_CLK_PLLARMA__PLLARM_NDIV_INT_R 8 +#define IHOST_PROC_CLK_PLLARMA__PLLARM_SOFT_POST_RESETB 1 +#define IHOST_PROC_CLK_PLLARMA__PLLARM_SOFT_RESETB 0 +#define IHOST_PROC_CLK_CORE0_CLKGATE 0X19000200 +#define IHOST_PROC_CLK_CORE1_CLKGATE 0X19000204 +#define IHOST_PROC_CLK_ARM_SWITCH_CLKGATE 0X19000210 +#define IHOST_PROC_CLK_ARM_PERIPH_CLKGATE 0X19000300 +#define IHOST_PROC_CLK_APB0_CLKGATE 0X19000400 +#define IPROC_CLKCT_HDELAY_SW_EN 0x00000303 + +#define IPROC_REG_WRITE_ACCESS 0x00a5a501 + +#define IPROC_PERIPH_BASE 0x19020000 +#define IPROC_PERIPH_INT_CTRL_REG_BASE (IPROC_PERIPH_BASE + 0x100) +#define IPROC_PERIPH_GLB_TIM_REG_BASE (IPROC_PERIPH_BASE + 0x200) +#define IPROC_PERIPH_PVT_TIM_REG_BASE (IPROC_PERIPH_BASE + 0x600) +#define IPROC_PERIPH_INT_DISTR_REG_BASE (IPROC_PERIPH_BASE + 0x1000) + +#define PLL_AXI_CLK 0x1DCD6500 + +#endif /* __SYSMAP_H */ |