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authorDinh Nguyen <dinguyen@opensource.altera.com>2015-10-15 10:13:36 -0500
committerMarek Vasut <marex@denx.de>2015-10-17 01:47:31 +0200
commit8d8e13e129f20ef82a271094eb713d513e83adf4 (patch)
tree04f4419564cb23a30063421916038f6accde3dd7 /arch/arm/include/asm/pl310.h
parent1275456d31cc130738775dca19b0a2ab1374cfbd (diff)
arm: socfpga: enable data/inst prefetch and shared override in the L2
Update the L2 AUX CTRL settings for the SoCFPGA. Enabling D and I prefetch bits helps improve SDRAM performance on the platform. Also, we need to enable bit 22 of the L2. By not having bit 22 set in the PL310 Auxiliary Control register (shared attribute override enable) has the side effect of transforming Normal Shared Non-cacheable reads into Cacheable no-allocate reads. Coherent DMA buffers in Linux always have a Cacheable alias via the kernel linear mapping and the processor can speculatively load cache lines into the PL310 controller. With bit 22 cleared, Non-cacheable reads would unexpectedly hit such cache lines leading to buffer corruption. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Diffstat (limited to 'arch/arm/include/asm/pl310.h')
-rw-r--r--arch/arm/include/asm/pl310.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h
index de7650eae7..d588f94350 100644
--- a/arch/arm/include/asm/pl310.h
+++ b/arch/arm/include/asm/pl310.h
@@ -17,6 +17,8 @@
#define L2X0_CTRL_EN 1
#define L310_SHARED_ATT_OVERRIDE_ENABLE (1 << 22)
+#define L310_AUX_CTRL_DATA_PREFETCH_MASK (1 << 28)
+#define L310_AUX_CTRL_INST_PREFETCH_MASK (1 << 29)
struct pl310_regs {
u32 pl310_cache_id;