diff options
| author | Shengzhou Liu <Shengzhou.Liu@nxp.com> | 2016-04-07 16:22:21 +0800 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-05-17 09:26:19 -0700 |
| commit | 074596c0b5f4e9a3642a3159a9fc7f8b8064c18a (patch) | |
| tree | 645933dc5c430f57d2c27ce98af98329d02852e0 /arch/arm/include/asm | |
| parent | aeaec0e682f45b9e0c62c522fafea353931f73ed (diff) | |
armv8/ls1043: Add workaround for DDR erratum A-008850
Barrier transactions from CCI400 need to be disabled till
the DDR is configured, otherwise it may lead to system hang.
The patch adds workaround to fix the erratum.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/include/asm')
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 10d17b2bef..a24dc2805d 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -191,6 +191,7 @@ #define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000 +#define CONFIG_SYS_FSL_ERRATUM_A008850 #define CONFIG_SYS_FSL_ERRATUM_A009663 #define CONFIG_SYS_FSL_ERRATUM_A009929 #define CONFIG_SYS_FSL_ERRATUM_A009942 |