diff options
| author | Tom Rini <trini@konsulko.com> | 2019-07-16 11:19:31 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-07-16 11:19:31 -0400 |
| commit | 0e80dda32c8d724c2a98dbbfb2f1e59762788f15 (patch) | |
| tree | a569b9b170c85a3bcae895c21c72def941ca9af9 /arch/arm/include/asm | |
| parent | 9c94e0a64490b90d48995a8230499167c0bdca68 (diff) | |
| parent | f96238e253661b43168352010a2628957940bd4b (diff) | |
Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-sunxi
- Beelink-x2 STB support (Marcus)
- H6 DDR3, LPDDR3 changes (Andre, Jernej)
- H6 pin controller, USB PHY (Andre)
Diffstat (limited to 'arch/arm/include/asm')
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h index eeb4da5c3f..0a1da02376 100644 --- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h +++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h @@ -9,6 +9,8 @@ #ifndef _SUNXI_DRAM_SUN50I_H6_H #define _SUNXI_DRAM_SUN50I_H6_H +#include <stdbool.h> + enum sunxi_dram_type { SUNXI_DRAM_TYPE_DDR3 = 3, SUNXI_DRAM_TYPE_DDR4, @@ -16,6 +18,11 @@ enum sunxi_dram_type { SUNXI_DRAM_TYPE_LPDDR3, }; +static inline bool sunxi_dram_is_lpddr(int type) +{ + return type >= SUNXI_DRAM_TYPE_LPDDR2; +} + /* * The following information is mainly retrieved by disassembly and some FPGA * test code of sun50iw3 platform. @@ -286,6 +293,32 @@ check_member(sunxi_mctl_phy_reg, dx[3].reserved_0xf0, 0xaf0); #define DCR_DDR3 (3 << 0) #define DCR_DDR4 (4 << 0) #define DCR_DDR8BANK BIT(3) +#define DCR_DDR2T BIT(28) + +/* + * The delay parameters allow to allegedly specify delay times of some + * unknown unit for each individual bit trace in each of the four data bytes + * the 32-bit wide access consists of. Also three control signals can be + * adjusted individually. + */ +#define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE) +/* The eight data lines (DQn) plus DM, DQS, DQS/DM/DQ Output Enable and DQSN */ +#define WR_LINES_PER_BYTE_LANE (BITS_PER_BYTE + 4) +/* + * The eight data lines (DQn) plus DM, DQS, DQS/DM/DQ Output Enable, DQSN, + * Termination and Power down + */ +#define RD_LINES_PER_BYTE_LANE (BITS_PER_BYTE + 6) +struct dram_para { + u32 clk; + enum sunxi_dram_type type; + u8 cols; + u8 rows; + u8 ranks; + const u8 dx_read_delays[NR_OF_BYTE_LANES][RD_LINES_PER_BYTE_LANE]; + const u8 dx_write_delays[NR_OF_BYTE_LANES][WR_LINES_PER_BYTE_LANE]; +}; + static inline int ns_to_t(int nanoseconds) { @@ -294,4 +327,6 @@ static inline int ns_to_t(int nanoseconds) return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000); } +void mctl_set_timing_params(struct dram_para *para); + #endif /* _SUNXI_DRAM_SUN50I_H6_H */ |