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| author | Tom Rini <trini@konsulko.com> | 2020-07-29 09:26:11 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-07-29 09:26:11 -0400 |
| commit | 423e08cb77015beab6a81595765ec1faa34bedde (patch) | |
| tree | 268fb246e025b8a5fc4eddc3c207ef428f16eb68 /arch/arm/include/asm | |
| parent | 3b191c56c841596771b4120f09fb556adf958b5c (diff) | |
| parent | 3fad1ca28d4c87346d18b89438bf2084fb2c3896 (diff) | |
Merge branch '2020-07-28-misc-soc-improvements'
- Assorted MediaTek improvements
- s5p4418 support
- QEMU ARM platform improvements
- Qualcomm IPQ40xx support
Diffstat (limited to 'arch/arm/include/asm')
| -rw-r--r-- | arch/arm/include/asm/system.h | 23 |
1 files changed, 19 insertions, 4 deletions
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 37c1bfd726..ce552944b7 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -445,10 +445,16 @@ static inline void set_dacr(unsigned int val) #define TTBCR_EPD0 (0 << 7) /* - * Memory types + * VMSAv8-32 Long-descriptor format memory region attributes + * (ARM Architecture Reference Manual section G5.7.4 [DDI0487E.a]) + * + * MAIR0[ 7: 0] 0x00 Device-nGnRnE (aka Strongly-Ordered) + * MAIR0[15: 8] 0xaa Outer/Inner Write-Through, Read-Allocate No Write-Allocate + * MAIR0[23:16] 0xee Outer/Inner Write-Back, Read-Allocate No Write-Allocate + * MAIR0[31:24] 0xff Outer/Inner Write-Back, Read-Allocate Write-Allocate */ -#define MEMORY_ATTRIBUTES ((0x00 << (0 * 8)) | (0x88 << (1 * 8)) | \ - (0xcc << (2 * 8)) | (0xff << (3 * 8))) +#define MEMORY_ATTRIBUTES ((0x00 << (0 * 8)) | (0xaa << (1 * 8)) | \ + (0xee << (2 * 8)) | (0xff << (3 * 8))) /* options available for data cache on each page */ enum dcache_option { @@ -471,7 +477,16 @@ enum dcache_option { #define TTB_SECT_B_MASK (1 << 2) #define TTB_SECT (2 << 0) -/* options available for data cache on each page */ +/* + * Short-descriptor format memory region attributes, without TEX remap + * (ARM Architecture Reference Manual section G5.7.2 [DDI0487E.a]) + * + * TEX[0] C B + * 0 0 0 Device-nGnRnE (aka Strongly-Ordered) + * 0 1 0 Outer/Inner Write-Through, Read-Allocate No Write-Allocate + * 0 1 1 Outer/Inner Write-Back, Read-Allocate No Write-Allocate + * 1 1 1 Outer/Inner Write-Back, Read-Allocate Write-Allocate + */ enum dcache_option { DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT, DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK, |