diff options
| author | Michal Simek <michal.simek@xilinx.com> | 2016-08-15 09:41:36 +0200 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2016-09-22 07:33:21 +0200 |
| commit | 48255f52764b64f35a268e4e87f2c3a621741836 (patch) | |
| tree | ebc561bc281755de0fa9f90017a18b1613f955fd /arch/arm/include/asm | |
| parent | d58fc12eb7f40a208e22b57037436411ea36125c (diff) | |
ARM64: zynqmp: Add support for USB ulpi phy reset via mode pins
Mode pins can be used as output for reset. Xilinx boards are using
this feature as additional way how to reset USB phys and also others
chips on the boards.
Mode1 is used on all these boards for this feature.
Let SPL toggle reset on this pin by default.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm/include/asm')
| -rw-r--r-- | arch/arm/include/asm/arch-zynqmp/hardware.h | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h index 10d67d0fb7..456c1b0902 100644 --- a/arch/arm/include/asm/arch-zynqmp/hardware.h +++ b/arch/arm/include/asm/arch-zynqmp/hardware.h @@ -25,6 +25,13 @@ #define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000 #define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000 +#define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT 0 +#define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT 8 + +#define PS_MODE0 BIT(0) +#define PS_MODE1 BIT(1) +#define PS_MODE2 BIT(2) +#define PS_MODE3 BIT(3) struct crlapb_regs { u32 reserved0[36]; @@ -35,7 +42,9 @@ struct crlapb_regs { u32 boot_mode; /* 0x200 */ u32 reserved3[14]; u32 rst_lpd_top; /* 0x23C */ - u32 reserved4[26]; + u32 reserved4[4]; + u32 boot_pin_ctrl; /* 0x250 */ + u32 reserved5[21]; }; #define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR) |