ARM: tegra: Tegra20 pinmux cleanup

This renames all the Tegra20 pinmux pins and functions so they have a
prefix which matches the type name.

The entries in tegra20_pingroups[] are all updated to remove the columns
which are no longer used.

All affected code is updated to match.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>

1 files changed, 131 insertions, 135 deletions

diff --git a/arch/arm/include/asm/arch-tegra20/pinmux.h b/arch/arm/include/asm/arch-tegra20/pinmux.h
index 328a3e3224..d7802d9675 100644
--- a/arch/arm/include/asm/arch-tegra20/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra20/pinmux.h
@@ -18,147 +18,145 @@
  */
 enum pmux_pingrp {
 	/* APB_MISC_PP_TRISTATE_REG_A_0 */
-	PINGRP_ATA,
-	PINGRP_ATB,
-	PINGRP_ATC,
-	PINGRP_ATD,
-	PINGRP_CDEV1,
-	PINGRP_CDEV2,
-	PINGRP_CSUS,
-	PINGRP_DAP1,
-
-	PINGRP_DAP2,
-	PINGRP_DAP3,
-	PINGRP_DAP4,
-	PINGRP_DTA,
-	PINGRP_DTB,
-	PINGRP_DTC,
-	PINGRP_DTD,
-	PINGRP_DTE,
-
-	PINGRP_GPU,
-	PINGRP_GPV,
-	PINGRP_I2CP,
-	PINGRP_IRTX,
-	PINGRP_IRRX,
-	PINGRP_KBCB,
-	PINGRP_KBCA,
-	PINGRP_PMC,
-
-	PINGRP_PTA,
-	PINGRP_RM,
-	PINGRP_KBCE,
-	PINGRP_KBCF,
-	PINGRP_GMA,
-	PINGRP_GMC,
-	PINGRP_SDIO1,
-	PINGRP_OWC,
+	PMUX_PINGRP_ATA,
+	PMUX_PINGRP_ATB,
+	PMUX_PINGRP_ATC,
+	PMUX_PINGRP_ATD,
+	PMUX_PINGRP_CDEV1,
+	PMUX_PINGRP_CDEV2,
+	PMUX_PINGRP_CSUS,
+	PMUX_PINGRP_DAP1,
+
+	PMUX_PINGRP_DAP2,
+	PMUX_PINGRP_DAP3,
+	PMUX_PINGRP_DAP4,
+	PMUX_PINGRP_DTA,
+	PMUX_PINGRP_DTB,
+	PMUX_PINGRP_DTC,
+	PMUX_PINGRP_DTD,
+	PMUX_PINGRP_DTE,
+
+	PMUX_PINGRP_GPU,
+	PMUX_PINGRP_GPV,
+	PMUX_PINGRP_I2CP,
+	PMUX_PINGRP_IRTX,
+	PMUX_PINGRP_IRRX,
+	PMUX_PINGRP_KBCB,
+	PMUX_PINGRP_KBCA,
+	PMUX_PINGRP_PMC,
+
+	PMUX_PINGRP_PTA,
+	PMUX_PINGRP_RM,
+	PMUX_PINGRP_KBCE,
+	PMUX_PINGRP_KBCF,
+	PMUX_PINGRP_GMA,
+	PMUX_PINGRP_GMC,
+	PMUX_PINGRP_SDIO1,
+	PMUX_PINGRP_OWC,
 
 	/* 32: APB_MISC_PP_TRISTATE_REG_B_0 */
-	PINGRP_GME,
-	PINGRP_SDC,
-	PINGRP_SDD,
-	PINGRP_RESERVED0,
-	PINGRP_SLXA,
-	PINGRP_SLXC,
-	PINGRP_SLXD,
-	PINGRP_SLXK,
-
-	PINGRP_SPDI,
-	PINGRP_SPDO,
-	PINGRP_SPIA,
-	PINGRP_SPIB,
-	PINGRP_SPIC,
-	PINGRP_SPID,
-	PINGRP_SPIE,
-	PINGRP_SPIF,
-
-	PINGRP_SPIG,
-	PINGRP_SPIH,
-	PINGRP_UAA,
-	PINGRP_UAB,
-	PINGRP_UAC,
-	PINGRP_UAD,
-	PINGRP_UCA,
-	PINGRP_UCB,
-
-	PINGRP_RESERVED1,
-	PINGRP_ATE,
-	PINGRP_KBCC,
-	PINGRP_RESERVED2,
-	PINGRP_RESERVED3,
-	PINGRP_GMB,
-	PINGRP_GMD,
-	PINGRP_DDC,
+	PMUX_PINGRP_GME,
+	PMUX_PINGRP_SDC,
+	PMUX_PINGRP_SDD,
+	PMUX_PINGRP_RESERVED0,
+	PMUX_PINGRP_SLXA,
+	PMUX_PINGRP_SLXC,
+	PMUX_PINGRP_SLXD,
+	PMUX_PINGRP_SLXK,
+
+	PMUX_PINGRP_SPDI,
+	PMUX_PINGRP_SPDO,
+	PMUX_PINGRP_SPIA,
+	PMUX_PINGRP_SPIB,
+	PMUX_PINGRP_SPIC,
+	PMUX_PINGRP_SPID,
+	PMUX_PINGRP_SPIE,
+	PMUX_PINGRP_SPIF,
+
+	PMUX_PINGRP_SPIG,
+	PMUX_PINGRP_SPIH,
+	PMUX_PINGRP_UAA,
+	PMUX_PINGRP_UAB,
+	PMUX_PINGRP_UAC,
+	PMUX_PINGRP_UAD,
+	PMUX_PINGRP_UCA,
+	PMUX_PINGRP_UCB,
+
+	PMUX_PINGRP_RESERVED1,
+	PMUX_PINGRP_ATE,
+	PMUX_PINGRP_KBCC,
+	PMUX_PINGRP_RESERVED2,
+	PMUX_PINGRP_RESERVED3,
+	PMUX_PINGRP_GMB,
+	PMUX_PINGRP_GMD,
+	PMUX_PINGRP_DDC,
 
 	/* 64: APB_MISC_PP_TRISTATE_REG_C_0 */
-	PINGRP_LD0,
-	PINGRP_LD1,
-	PINGRP_LD2,
-	PINGRP_LD3,
-	PINGRP_LD4,
-	PINGRP_LD5,
-	PINGRP_LD6,
-	PINGRP_LD7,
-
-	PINGRP_LD8,
-	PINGRP_LD9,
-	PINGRP_LD10,
-	PINGRP_LD11,
-	PINGRP_LD12,
-	PINGRP_LD13,
-	PINGRP_LD14,
-	PINGRP_LD15,
-
-	PINGRP_LD16,
-	PINGRP_LD17,
-	PINGRP_LHP0,
-	PINGRP_LHP1,
-	PINGRP_LHP2,
-	PINGRP_LVP0,
-	PINGRP_LVP1,
-	PINGRP_HDINT,
-
-	PINGRP_LM0,
-	PINGRP_LM1,
-	PINGRP_LVS,
-	PINGRP_LSC0,
-	PINGRP_LSC1,
-	PINGRP_LSCK,
-	PINGRP_LDC,
-	PINGRP_LCSN,
+	PMUX_PINGRP_LD0,
+	PMUX_PINGRP_LD1,
+	PMUX_PINGRP_LD2,
+	PMUX_PINGRP_LD3,
+	PMUX_PINGRP_LD4,
+	PMUX_PINGRP_LD5,
+	PMUX_PINGRP_LD6,
+	PMUX_PINGRP_LD7,
+
+	PMUX_PINGRP_LD8,
+	PMUX_PINGRP_LD9,
+	PMUX_PINGRP_LD10,
+	PMUX_PINGRP_LD11,
+	PMUX_PINGRP_LD12,
+	PMUX_PINGRP_LD13,
+	PMUX_PINGRP_LD14,
+	PMUX_PINGRP_LD15,
+
+	PMUX_PINGRP_LD16,
+	PMUX_PINGRP_LD17,
+	PMUX_PINGRP_LHP0,
+	PMUX_PINGRP_LHP1,
+	PMUX_PINGRP_LHP2,
+	PMUX_PINGRP_LVP0,
+	PMUX_PINGRP_LVP1,
+	PMUX_PINGRP_HDINT,
+
+	PMUX_PINGRP_LM0,
+	PMUX_PINGRP_LM1,
+	PMUX_PINGRP_LVS,
+	PMUX_PINGRP_LSC0,
+	PMUX_PINGRP_LSC1,
+	PMUX_PINGRP_LSCK,
+	PMUX_PINGRP_LDC,
+	PMUX_PINGRP_LCSN,
 
 	/* 96: APB_MISC_PP_TRISTATE_REG_D_0 */
-	PINGRP_LSPI,
-	PINGRP_LSDA,
-	PINGRP_LSDI,
-	PINGRP_LPW0,
-	PINGRP_LPW1,
-	PINGRP_LPW2,
-	PINGRP_LDI,
-	PINGRP_LHS,
-
-	PINGRP_LPP,
-	PINGRP_RESERVED4,
-	PINGRP_KBCD,
-	PINGRP_GPU7,
-	PINGRP_DTF,
-	PINGRP_UDA,
-	PINGRP_CRTP,
-	PINGRP_SDB,
+	PMUX_PINGRP_LSPI,
+	PMUX_PINGRP_LSDA,
+	PMUX_PINGRP_LSDI,
+	PMUX_PINGRP_LPW0,
+	PMUX_PINGRP_LPW1,
+	PMUX_PINGRP_LPW2,
+	PMUX_PINGRP_LDI,
+	PMUX_PINGRP_LHS,
+
+	PMUX_PINGRP_LPP,
+	PMUX_PINGRP_RESERVED4,
+	PMUX_PINGRP_KBCD,
+	PMUX_PINGRP_GPU7,
+	PMUX_PINGRP_DTF,
+	PMUX_PINGRP_UDA,
+	PMUX_PINGRP_CRTP,
+	PMUX_PINGRP_SDB,
 
 	/* these pin groups only have pullup and pull down control */
-	PINGRP_FIRST_NO_MUX,
-	PINGRP_CK32 = PINGRP_FIRST_NO_MUX,
-	PINGRP_DDRC,
-	PINGRP_PMCA,
-	PINGRP_PMCB,
-	PINGRP_PMCC,
-	PINGRP_PMCD,
-	PINGRP_PMCE,
-	PINGRP_XM2C,
-	PINGRP_XM2D,
-
+	PMUX_PINGRP_CK32,
+	PMUX_PINGRP_DDRC,
+	PMUX_PINGRP_PMCA,
+	PMUX_PINGRP_PMCB,
+	PMUX_PINGRP_PMCC,
+	PMUX_PINGRP_PMCD,
+	PMUX_PINGRP_PMCE,
+	PMUX_PINGRP_XM2C,
+	PMUX_PINGRP_XM2D,
 	PMUX_PINGRP_COUNT,
 };
 
@@ -227,9 +225,7 @@ enum pmux_func {
 	PMUX_FUNC_VI,
 	PMUX_FUNC_VI_SENSOR_CLK,
 	PMUX_FUNC_XIO,
-
 	PMUX_FUNC_COUNT,
-
 	PMUX_FUNC_RSVD1 = 0x8000,
 	PMUX_FUNC_RSVD2 = 0x8001,
 	PMUX_FUNC_RSVD3 = 0x8002,