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authorMikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com>2012-07-09 08:52:41 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-09-01 14:58:10 +0200
commit89473d233f0d8ef74c6aac37fe3258ef3d3efc06 (patch)
treec798a414e8c103be95166def21606b5179f44c17 /arch/arm/include/asm
parentc50afc1dab78a1a72bc37b60d97864e56b52cc5c (diff)
arm/davinci: fix DDR2/mDDR memory controller initialization for Omap L138
follow section 15.2.13.1 (Initializing Following Device Power Up or Reset) of OMAP-L138 DSP+ARM Processor Technical Reference Manual Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com> Acked-by: Christian Riesch <christian.riesch@omicron.at> Tested-by: Christian Riesch <christian.riesch@omicron.at>
Diffstat (limited to 'arch/arm/include/asm')
-rw-r--r--arch/arm/include/asm/arch-davinci/hardware.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h
index f6b7a2caef..acb0fe2339 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -506,6 +506,7 @@ struct davinci_syscfg1_regs {
((struct davinci_syscfg1_regs *)DAVINCI_SYSCFG1_BASE)
#define DDR_SLEW_CMOSEN_BIT 4
+#define DDR_SLEW_DDR_PDENA_BIT 5
#define VTP_POWERDWN (1 << 6)
#define VTP_LOCK (1 << 7)