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authorAmit Singh Tomar <amittomer25@gmail.com>2016-07-06 17:59:44 +0530
committerHans de Goede <hdegoede@redhat.com>2016-07-15 08:34:34 +0200
commita29710c525ff43c3031b879e2beac306a09c6944 (patch)
treee132b91dc6c3a28dd0079ff029a7b00776445883 /arch/arm/include/asm
parent26c0c15786039fb437925c08205702169462e343 (diff)
net: Add EMAC driver for H3/A83T/A64 SoCs.
This patch add EMAC driver support for H3/A83T/A64 SoCs. Tested on Pine64(A64-External PHY) and Orangepipc(H3-Internal PHY). BIG Thanks to Andre for providing some of the DT code. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Diffstat (limited to 'arch/arm/include/asm')
-rw-r--r--arch/arm/include/asm/arch-sunxi/clock_sun6i.h4
-rw-r--r--arch/arm/include/asm/arch-sunxi/cpu_sun4i.h3
2 files changed, 5 insertions, 2 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index c2e72f5a86..d4dff1e346 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -40,7 +40,8 @@ struct sunxi_ccm_reg {
u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */
u32 apb1_gate; /* 0x68 apb1 module clock gating */
u32 apb2_gate; /* 0x6c apb2 module clock gating */
- u32 reserved9[4];
+ u32 bus_gate4; /* 0x70 gate 4 module clock gating */
+ u8 res3[0xc];
u32 nand0_clk_cfg; /* 0x80 nand0 clock control */
u32 nand1_clk_cfg; /* 0x84 nand1 clock control */
u32 sd0_clk_cfg; /* 0x88 sd0 clock control */
@@ -387,6 +388,7 @@ struct sunxi_ccm_reg {
#define AHB_RESET_OFFSET_LCD0 4
/* ahb_reset2 offsets */
+#define AHB_RESET_OFFSET_EPHY 2
#define AHB_RESET_OFFSET_LVDS 0
/* apb2 reset */
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index c5e9d88bab..cd009d7ccc 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -87,7 +87,8 @@
#define SUNXI_KEYPAD_BASE 0x01c23000
#define SUNXI_TZPC_BASE 0x01c23400
-#if defined(CONFIG_MACH_SUN8I_A83T) || defined(CONFIG_MACH_SUN8I_H3)
+#if defined(CONFIG_MACH_SUN8I_A83T) || defined(CONFIG_MACH_SUN8I_H3) || \
+defined(CONFIG_MACH_SUN50I)
/* SID address space starts at 0x01c1400, but e-fuse is at offset 0x200 */
#define SUNXI_SID_BASE 0x01c14200
#else