diff options
| author | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2014-05-16 16:49:50 +0200 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2014-05-16 16:49:50 +0200 |
| commit | a90bed77a6ec51cf8032a4d731014f9381ec6466 (patch) | |
| tree | c66f624614edd0ee3bb7f0c72e574d6258978a4e /arch/arm/include/asm | |
| parent | 44cfc3a83f2a62963af2de8d983daf4c77e1db0c (diff) | |
| parent | 97eeae1a0735fc17351f10b9978e966392badedc (diff) | |
Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'
Diffstat (limited to 'arch/arm/include/asm')
| -rw-r--r-- | arch/arm/include/asm/arch-am33xx/clock.h | 2 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-omap5/clock.h | 3 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-omap5/omap.h | 1 |
3 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h index 7637457549..f00fad38fe 100644 --- a/arch/arm/include/asm/arch-am33xx/clock.h +++ b/arch/arm/include/asm/arch-am33xx/clock.h @@ -42,6 +42,8 @@ #define MODULE_CLKCTRL_IDLEST_DISABLED 3 /* CM_CLKMODE_DPLL */ +#define CM_CLKMODE_DPLL_SSC_EN_SHIFT 12 +#define CM_CLKMODE_DPLL_SSC_EN_MASK (1 << 12) #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 #define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) #define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10 diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index 2dfe4efb4b..30d9de2764 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -322,6 +322,9 @@ #define V_SCLK V_OSCK +/* CKO buffer control */ +#define CKOBUFFER_CLK_ENABLE_MASK (1 << 28) + /* AUXCLKx reg fields */ #define AUXCLK_ENABLE_MASK (1 << 8) #define AUXCLK_SRCSELECT_SHIFT 1 diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 19fdecec01..e35a81a8af 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -50,6 +50,7 @@ #define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000) #define UART2_BASE (OMAP54XX_L4_PER_BASE + 0x6c000) #define UART3_BASE (OMAP54XX_L4_PER_BASE + 0x20000) +#define UART4_BASE (OMAP54XX_L4_PER_BASE + 0x6e000) /* General Purpose Timers */ #define GPT1_BASE (OMAP54XX_L4_WKUP_BASE + 0x18000) |