diff options
| author | Chander Kashyap <chander.kashyap@linaro.org> | 2012-12-25 20:13:38 +0000 |
|---|---|---|
| committer | Minkyu Kang <mk7.kang@samsung.com> | 2012-12-26 16:16:02 +0900 |
| commit | b189a83a08d8e2690ab71fa50303c76fe259f007 (patch) | |
| tree | f8f0c69c62a35e37230eac2bda77e9e7655a4167 /arch/arm/include/asm | |
| parent | 96764df1b47ddebfb50fadf5af72530b07b5fc89 (diff) | |
EXYNOS: EXYNOS4X12: Populate Exynos4x12 register addresses
This patch populates base addresses of Exynos4x12 registers.
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'arch/arm/include/asm')
| -rw-r--r-- | arch/arm/include/asm/arch-exynos/cpu.h | 48 |
1 files changed, 42 insertions, 6 deletions
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index f06af2eb85..eb34422353 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -27,7 +27,7 @@ #define EXYNOS_CPU_NAME "Exynos" #define EXYNOS4_ADDR_BASE 0x10000000 -/* EXYNOS4 */ +/* EXYNOS4 Common*/ #define EXYNOS4_I2C_SPACING 0x10000 #define EXYNOS4_GPIO_PART3_BASE 0x03860000 @@ -63,7 +63,40 @@ #define EXYNOS4_DP_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4_SPI_ISP_BASE DEVICE_NOT_AVAILABLE -/* EXYNOS5 */ +/* EXYNOS4X12 */ +#define EXYNOS4X12_GPIO_PART3_BASE 0x03860000 +#define EXYNOS4X12_PRO_ID 0x10000000 +#define EXYNOS4X12_SYSREG_BASE 0x10010000 +#define EXYNOS4X12_POWER_BASE 0x10020000 +#define EXYNOS4X12_SWRESET 0x10020400 +#define EXYNOS4X12_USBPHY_CONTROL 0x10020704 +#define EXYNOS4X12_CLOCK_BASE 0x10030000 +#define EXYNOS4X12_SYSTIMER_BASE 0x10050000 +#define EXYNOS4X12_WATCHDOG_BASE 0x10060000 +#define EXYNOS4X12_DMC0_BASE 0x10600000 +#define EXYNOS4X12_DMC1_BASE 0x10610000 +#define EXYNOS4X12_GPIO_PART4_BASE 0x106E0000 +#define EXYNOS4X12_GPIO_PART2_BASE 0x11000000 +#define EXYNOS4X12_GPIO_PART1_BASE 0x11400000 +#define EXYNOS4X12_FIMD_BASE 0x11C00000 +#define EXYNOS4X12_MIPI_DSIM_BASE 0x11C80000 +#define EXYNOS4X12_USBOTG_BASE 0x12480000 +#define EXYNOS4X12_MMC_BASE 0x12510000 +#define EXYNOS4X12_SROMC_BASE 0x12570000 +#define EXYNOS4X12_USB_HOST_EHCI_BASE 0x12580000 +#define EXYNOS4X12_USBPHY_BASE 0x125B0000 +#define EXYNOS4X12_UART_BASE 0x13800000 +#define EXYNOS4X12_I2C_BASE 0x13860000 +#define EXYNOS4X12_PWMTIMER_BASE 0x139D0000 + +#define EXYNOS4X12_ADC_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4X12_DP_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4X12_MODEM_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4X12_I2S_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4X12_SPI_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4X12_SPI_ISP_BASE DEVICE_NOT_AVAILABLE + +/* EXYNOS5 Common*/ #define EXYNOS5_I2C_SPACING 0x10000 #define EXYNOS5_GPIO_PART4_BASE 0x03860000 @@ -154,17 +187,20 @@ static inline int proid_is_##type(void) \ } IS_EXYNOS_TYPE(exynos4210, 0x4210) +IS_EXYNOS_TYPE(exynos4412, 0x4412) IS_EXYNOS_TYPE(exynos5250, 0x5250) #define SAMSUNG_BASE(device, base) \ static inline unsigned int samsung_get_base_##device(void) \ { \ - if (cpu_is_exynos4()) \ + if (cpu_is_exynos4()) { \ + if (proid_is_exynos4412()) \ + return EXYNOS4X12_##base; \ return EXYNOS4_##base; \ - else if (cpu_is_exynos5()) \ + } else if (cpu_is_exynos5()) { \ return EXYNOS5_##base; \ - else \ - return 0; \ + } \ + return 0; \ } SAMSUNG_BASE(adc, ADC_BASE) |