diff options
| author | Peng Fan <peng.fan@nxp.com> | 2018-11-20 10:19:32 +0000 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2019-01-01 14:12:18 +0100 |
| commit | b3e5cb8d3594817326819127fb4942aa39914003 (patch) | |
| tree | 088cf6479856e79524e2b1150700f1938fcd97d5 /arch/arm/include/asm | |
| parent | 278f273c5681db3c158faa23deb3fb69801d3cab (diff) | |
imx: imx8m: clock refactor dram pll part
Refactor dram_pll_init to accept args to configure different pll freq.
Introduce dram_enable_bypass and dram_disable_bypass
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'arch/arm/include/asm')
| -rw-r--r-- | arch/arm/include/asm/arch-imx8m/clock.h | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-imx8m/clock.h b/arch/arm/include/asm/arch-imx8m/clock.h index 45cfea3018..e7c1670f6b 100644 --- a/arch/arm/include/asm/arch-imx8m/clock.h +++ b/arch/arm/include/asm/arch-imx8m/clock.h @@ -10,6 +10,8 @@ #include <linux/bitops.h> +#define MHZ(X) ((X) * 1000000UL) + enum pll_clocks { ANATOP_ARM_PLL, ANATOP_GPU_PLL, @@ -631,6 +633,26 @@ enum frac_pll_out_val { FRAC_PLL_OUT_1600M, }; +#define DRAM_BYPASS_ROOT_CONFIG(_rate, _m, _p, _s, _k) \ + { \ + .clk = (_rate), \ + .alt_root_sel = (_m), \ + .alt_pre_div = (_p), \ + .apb_root_sel = (_s), \ + .apb_pre_div = (_k), \ + } + +struct dram_bypass_clk_setting { + ulong clk; + int alt_root_sel; + enum root_pre_div alt_pre_div; + int apb_root_sel; + enum root_pre_div apb_pre_div; +}; + +void dram_pll_init(ulong pll_val); +void dram_enable_bypass(ulong clk_val); +void dram_disable_bypass(void); u32 imx_get_fecclk(void); u32 imx_get_uartclk(void); int clock_init(void); |