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authorTom Rini <trini@konsulko.com>2016-08-26 14:58:52 -0400
committerTom Rini <trini@konsulko.com>2016-08-26 17:05:01 -0400
commitc6b968da78ce3fa7224c0ddf15fe170c7c05b27e (patch)
tree42716ddc52ec9caecc19588a2d0c5ca9a94188dd /arch/arm/include/asm
parent1cfce74fe5a2301ee9b384d9395ba95db930c9d6 (diff)
parentd5ac6eef91965b519d8f15f17febfa0ea2ee0adc (diff)
Merge branch 'master' of http://git.denx.de/u-boot-sunxi
Diffstat (limited to 'arch/arm/include/asm')
-rw-r--r--arch/arm/include/asm/arch-sunxi/clock_sun6i.h9
-rw-r--r--arch/arm/include/asm/arch-sunxi/cpu_sun4i.h7
-rw-r--r--arch/arm/include/asm/arch-sunxi/gpio.h3
-rw-r--r--arch/arm/include/asm/arch-sunxi/pwm.h34
4 files changed, 52 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index d4dff1e346..be9fcfda0e 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -116,7 +116,9 @@ struct sunxi_ccm_reg {
u32 mipi_bias_cfg; /* 0x240 MIPI Bias config */
u32 pll9_bias_cfg; /* 0x244 PLL9 Bias config */
u32 pll10_bias_cfg; /* 0x248 PLL10 Bias config */
- u32 reserved21[13];
+ u32 reserved21[5];
+ u32 pll5_tuning_cfg; /* 0x260 PLL5 Tuning config */
+ u32 reserved21_5[7];
u32 pll1_pattern_cfg; /* 0x280 PLL1 Pattern config */
u32 pll2_pattern_cfg; /* 0x284 PLL2 Pattern config */
u32 pll3_pattern_cfg; /* 0x288 PLL3 Pattern config */
@@ -223,6 +225,11 @@ struct sunxi_ccm_reg {
#define CCM_PLL11_CTRL_UPD (0x1 << 30)
#define CCM_PLL11_CTRL_EN (0x1 << 31)
+#define CCM_PLL5_TUN_LOCK_TIME(x) (((x) & 0x7) << 24)
+#define CCM_PLL5_TUN_LOCK_TIME_MASK CCM_PLL5_TUN_LOCK_TIME(0x7)
+#define CCM_PLL5_TUN_INIT_FREQ(x) (((x) & 0x7f) << 16)
+#define CCM_PLL5_TUN_INIT_FREQ_MASK CCM_PLL5_TUN_INIT_FREQ(0x7f)
+
#if defined(CONFIG_MACH_SUN50I)
/* AHB1=100MHz failsafe setup from the FEL mode, usable with PMIC defaults */
#define AHB1_ABP1_DIV_DEFAULT 0x00003190 /* AHB1=PLL6/6,APB1=AHB1/2 */
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index cd009d7ccc..5f93830915 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -76,8 +76,15 @@
#define SUNXI_INTC_BASE 0x01c20400
#define SUNXI_PIO_BASE 0x01c20800
#define SUNXI_TIMER_BASE 0x01c20c00
+#ifndef CONFIG_SUNXI_GEN_SUN6I
+#define SUNXI_PWM_BASE 0x01c20e00
+#endif
#define SUNXI_SPDIF_BASE 0x01c21000
+#ifdef CONFIG_SUNXI_GEN_SUN6I
+#define SUNXI_PWM_BASE 0x01c21400
+#else
#define SUNXI_AC97_BASE 0x01c21400
+#endif
#define SUNXI_IR0_BASE 0x01c21800
#define SUNXI_IR1_BASE 0x01c21c00
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index bff7d1453f..85a4ec3b0e 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -150,6 +150,7 @@ enum sunxi_gpio_number {
#define SUN6I_GPA_SDC3 4
#define SUN8I_H3_GPA_UART0 2
+#define SUN4I_GPB_PWM 2
#define SUN4I_GPB_TWI0 2
#define SUN4I_GPB_TWI1 2
#define SUN5I_GPB_TWI1 2
@@ -186,6 +187,8 @@ enum sunxi_gpio_number {
#define SUN6I_GPG_TWI3 2
#define SUN5I_GPG_UART1 4
+#define SUN6I_GPH_PWM 2
+#define SUN8I_GPH_PWM 2
#define SUN4I_GPH_SDC1 5
#define SUN6I_GPH_TWI0 2
#define SUN8I_GPH_TWI0 2
diff --git a/arch/arm/include/asm/arch-sunxi/pwm.h b/arch/arm/include/asm/arch-sunxi/pwm.h
new file mode 100644
index 0000000000..5884b5dbe7
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/pwm.h
@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2016 Hans de Goede <hdegoede@redhat.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SUNXI_PWM_H
+#define _SUNXI_PWM_H
+
+#define SUNXI_PWM_CTRL_REG (SUNXI_PWM_BASE + 0)
+#define SUNXI_PWM_CH0_PERIOD (SUNXI_PWM_BASE + 4)
+
+#define SUNXI_PWM_CTRL_PRESCALE0(x) ((x) & 0xf)
+#define SUNXI_PWM_CTRL_ENABLE0 (0x5 << 4)
+#define SUNXI_PWM_CTRL_POLARITY0(x) ((x) << 5)
+
+#define SUNXI_PWM_PERIOD_80PCT 0x04af03c0
+
+#if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN5I
+#define SUNXI_PWM_PIN0 SUNXI_GPB(2)
+#define SUNXI_PWM_MUX SUN4I_GPB_PWM
+#endif
+
+#if defined CONFIG_MACH_SUN6I
+#define SUNXI_PWM_PIN0 SUNXI_GPH(13)
+#define SUNXI_PWM_MUX SUN6I_GPH_PWM
+#endif
+
+#if defined CONFIG_MACH_SUN8I_A23 || defined CONFIG_MACH_SUN8I_A33
+#define SUNXI_PWM_PIN0 SUNXI_GPH(0)
+#define SUNXI_PWM_MUX SUN8I_GPH_PWM
+#endif
+
+#endif