diff options
| author | Tom Rini <trini@ti.com> | 2012-07-24 13:05:10 -0700 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-09-01 14:58:12 +0200 |
| commit | c8da4a587c5aaa070096db923ac45e5cf5d97ceb (patch) | |
| tree | a56bec13ca4dce23d2c6878a2f804e73623b650c /arch/arm/include/asm | |
| parent | b971dfad6a1c8c37857390d847ee22ec7af4aee2 (diff) | |
am33xx: Clean up unused DDR defines, prefix more with 'DDR2'
- Remove a handful of unused defines.
- Prefix more values with 'DDR2' as DDR3 will require different values.
Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm/include/asm')
| -rw-r--r-- | arch/arm/include/asm/arch-am33xx/ddr_defs.h | 32 |
1 files changed, 12 insertions, 20 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 842e45f559..b4735bac21 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -22,38 +22,30 @@ #include <asm/arch/hardware.h> /* AM335X EMIF Register values */ -#define EMIF_SDMGT 0x80000000 -#define EMIF_SDRAM 0x00004650 -#define EMIF_PHYCFG 0x2 -#define DDR_PHY_RESET (0x1 << 10) -#define DDR_FUNCTIONAL_MODE_EN 0x1 -#define DDR_PHY_READY (0x1 << 2) #define VTP_CTRL_READY (0x1 << 5) #define VTP_CTRL_ENABLE (0x1 << 6) -#define VTP_CTRL_LOCK_EN (0x1 << 4) #define VTP_CTRL_START_EN (0x1) -#define DDR2_RATIO 0x80 #define CMD_FORCE 0x00 #define CMD_DELAY 0x00 +#define PHY_DLL_LOCK_DIFF 0x0 -#define EMIF_READ_LATENCY 0x05 -#define EMIF_TIM1 0x0666B3D6 -#define EMIF_TIM2 0x143731DA -#define EMIF_TIM3 0x00000347 -#define EMIF_SDCFG 0x43805332 -#define EMIF_SDREF 0x0000081a +#define DDR2_EMIF_READ_LATENCY 0x05 +#define DDR2_EMIF_TIM1 0x0666B3D6 +#define DDR2_EMIF_TIM2 0x143731DA +#define DDR2_EMIF_TIM3 0x00000347 +#define DDR2_EMIF_SDCFG 0x43805332 +#define DDR2_EMIF_SDREF 0x0000081a #define DDR2_DLL_LOCK_DIFF 0x0 -#define DDR2_RD_DQS 0x12 -#define DDR2_PHY_FIFO_WE 0x80 - +#define DDR2_RATIO 0x80 #define DDR2_INVERT_CLKOUT 0x00 +#define DDR2_RD_DQS 0x12 #define DDR2_WR_DQS 0x00 #define DDR2_PHY_WRLVL 0x00 #define DDR2_PHY_GATELVL 0x00 #define DDR2_PHY_WR_DATA 0x40 -#define PHY_RANK0_DELAY 0x01 -#define PHY_DLL_LOCK_DIFF 0x0 -#define DDR_IOCTRL_VALUE 0x18B +#define DDR2_PHY_FIFO_WE 0x80 +#define DDR2_PHY_RANK0_DELAY 0x1 +#define DDR2_IOCTRL_VALUE 0x18B /** * Encapsulates DDR PHY control and corresponding shadow registers. |