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authorNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>2014-10-31 16:08:11 +0900
committerNobuhiro Iwamatsu <iwamatsu@nigauri.org>2014-11-04 08:58:23 +0900
commitd8659c6d25219e3f89b6696b86c3b18dcf5c3fb5 (patch)
tree68612b75bf9eee938b4c496cb2d5ba66502251f0 /arch/arm/include/asm
parent3372a9a7a83ca62f5d3536afef8aec6ac553ad9e (diff)
arm: rmobile: lager: Fix change of the CPU frequency
The change of the CPU frequency is waited for until PLL0ST of the PLLECR is set to 1. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'arch/arm/include/asm')
-rw-r--r--arch/arm/include/asm/arch-rmobile/rcar-base.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-rmobile/rcar-base.h b/arch/arm/include/asm/arch-rmobile/rcar-base.h
index 027e9b1b14..9c1439b764 100644
--- a/arch/arm/include/asm/arch-rmobile/rcar-base.h
+++ b/arch/arm/include/asm/arch-rmobile/rcar-base.h
@@ -385,6 +385,8 @@
#define PLL0CR 0xE61500D8
#define PLL0_STC_MASK 0x7F000000
#define PLL0_STC_BIT 24
+#define PLLECR 0xE61500D0
+#define PLL0ST 0x100
#ifndef __ASSEMBLY__
#include <asm/types.h>