net: gmac_rockchip: Add support for the RK3399 GMAC

The GMAC in the RK3399 is very similar to the RK3288 variant (i.e. it
is a Designware GMAC core and requires similar configuration as the
RK3288 to switch it to RGMII and set up the TX/RX delays for Gigabit).
The key difference is that the register offsets (within the GRF block)
and bit-offsets (within those registers) used to hold the configuration
differ between the various RK32/33 CPUs.

This change refactors the gmac_rockchip.c driver to use a function
table (selected via driver_data) to factor out these differences. Each
function's implementation then matches the underlying processor.

Some collateral changes are needed in the definitions describing the
bits and offsets in the GRF are needed to prefix each set of symbolic
constants with the SoC name to avoid name clashes... and in doing so,
the shifts for masks and constants have been moved into the header
files for readability (and to make it easier to stay below 80 chars).

X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
Fixed commit message typo s/factor our/factor out/:
Signed-off-by: Simon Glass <sjg@chromium.org>

2 files changed, 82 insertions, 33 deletions

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
index aaffd19dea..1a7c8199c3 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
@@ -720,20 +720,20 @@ enum {
 
 /* GRF_SOC_CON1 */
 enum {
-	RMII_MODE_SHIFT = 0xe,
-	RMII_MODE_MASK = 1,
-	RMII_MODE = 1,
+	RK3288_RMII_MODE_SHIFT = 14,
+	RK3288_RMII_MODE_MASK  = (1 << RK3288_RMII_MODE_SHIFT),
+	RK3288_RMII_MODE       = (1 << RK3288_RMII_MODE_SHIFT),
 
-	GMAC_CLK_SEL_SHIFT	= 0xc,
-	GMAC_CLK_SEL_MASK	= 3,
-	GMAC_CLK_SEL_125M	= 0,
-	GMAC_CLK_SEL_25M	= 0x3,
-	GMAC_CLK_SEL_2_5M	= 0x2,
+	RK3288_GMAC_CLK_SEL_SHIFT = 12,
+	RK3288_GMAC_CLK_SEL_MASK  = (3 << RK3288_GMAC_CLK_SEL_SHIFT),
+	RK3288_GMAC_CLK_SEL_125M  = (0 << RK3288_GMAC_CLK_SEL_SHIFT),
+	RK3288_GMAC_CLK_SEL_25M   = (3 << RK3288_GMAC_CLK_SEL_SHIFT),
+	RK3288_GMAC_CLK_SEL_2_5M  = (2 << RK3288_GMAC_CLK_SEL_SHIFT),
 
-	RMII_CLK_SEL_SHIFT	= 0xb,
-	RMII_CLK_SEL_MASK	= 1,
-	RMII_CLK_SEL_2_5M	= 0,
-	RMII_CLK_SEL_25M,
+	RK3288_RMII_CLK_SEL_SHIFT = 11,
+	RK3288_RMII_CLK_SEL_MASK  = (1 << RK3288_RMII_CLK_SEL_SHIFT),
+	RK3288_RMII_CLK_SEL_2_5M  = (0 << RK3288_RMII_CLK_SEL_SHIFT),
+	RK3288_RMII_CLK_SEL_25M   = (1 << RK3288_RMII_CLK_SEL_SHIFT),
 
 	GMAC_SPEED_SHIFT	= 0xa,
 	GMAC_SPEED_MASK		= 1,
@@ -743,10 +743,10 @@ enum {
 	GMAC_FLOWCTRL_SHIFT	= 0x9,
 	GMAC_FLOWCTRL_MASK	= 1,
 
-	GMAC_PHY_INTF_SEL_SHIFT	= 0x6,
-	GMAC_PHY_INTF_SEL_MASK	= 0x7,
-	GMAC_PHY_INTF_SEL_RGMII	= 0x1,
-	GMAC_PHY_INTF_SEL_RMII	= 0x4,
+	RK3288_GMAC_PHY_INTF_SEL_SHIFT = 6,
+	RK3288_GMAC_PHY_INTF_SEL_MASK  = (7 << RK3288_GMAC_PHY_INTF_SEL_SHIFT),
+	RK3288_GMAC_PHY_INTF_SEL_RGMII = (1 << RK3288_GMAC_PHY_INTF_SEL_SHIFT),
+	RK3288_GMAC_PHY_INTF_SEL_RMII  = (4 << RK3288_GMAC_PHY_INTF_SEL_SHIFT),
 
 	HOST_REMAP_SHIFT	= 0x5,
 	HOST_REMAP_MASK		= 1
@@ -801,21 +801,27 @@ enum {
 
 /* GRF_SOC_CON3 */
 enum {
-	RXCLK_DLY_ENA_GMAC_SHIFT	= 0xf,
-	RXCLK_DLY_ENA_GMAC_MASK		= 1,
-	RXCLK_DLY_ENA_GMAC_DISABLE	= 0,
-	RXCLK_DLY_ENA_GMAC_ENABLE,
-
-	TXCLK_DLY_ENA_GMAC_SHIFT	= 0xe,
-	TXCLK_DLY_ENA_GMAC_MASK		= 1,
-	TXCLK_DLY_ENA_GMAC_DISABLE	= 0,
-	TXCLK_DLY_ENA_GMAC_ENABLE,
-
-	CLK_RX_DL_CFG_GMAC_SHIFT	= 0x7,
-	CLK_RX_DL_CFG_GMAC_MASK		= 0x7f,
-
-	CLK_TX_DL_CFG_GMAC_SHIFT	= 0x0,
-	CLK_TX_DL_CFG_GMAC_MASK		= 0x7f,
+	RK3288_RXCLK_DLY_ENA_GMAC_SHIFT = 0xf,
+	RK3288_RXCLK_DLY_ENA_GMAC_MASK =
+		(1 << RK3288_RXCLK_DLY_ENA_GMAC_SHIFT),
+	RK3288_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
+	RK3288_RXCLK_DLY_ENA_GMAC_ENABLE =
+		(1 << RK3288_RXCLK_DLY_ENA_GMAC_SHIFT),
+
+	RK3288_TXCLK_DLY_ENA_GMAC_SHIFT = 0xe,
+	RK3288_TXCLK_DLY_ENA_GMAC_MASK =
+		(1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT),
+	RK3288_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
+	RK3288_TXCLK_DLY_ENA_GMAC_ENABLE =
+		(1 << RK3288_RXCLK_DLY_ENA_GMAC_SHIFT),
+
+	RK3288_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
+	RK3288_CLK_RX_DL_CFG_GMAC_MASK =
+		(0x7f << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT),
+
+	RK3288_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
+	RK3288_CLK_TX_DL_CFG_GMAC_MASK =
+		(0x7f << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT),
 };
 
 #endif
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
index e709fdaad2..b340b05e36 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
@@ -144,7 +144,9 @@ struct rk3399_grf_regs {
 	};
 	u32 gpio4d_iomux;
 	u32 reserved21[4];
-	u32 gpio2_p[3][4];
+	u32 gpio2_p[4];
+	u32 gpio3_p[4];
+	u32 gpio4_p[4];
 	u32 reserved22[4];
 	u32 gpio2_sr[3][4];
 	u32 reserved23[4];
@@ -215,7 +217,9 @@ struct rk3399_pmugrf_regs {
 	};
 	u32 gpio1d_iomux;
 	u32 reserved1[8];
-	u32 gpio0_p[2][4];
+	u32 gpio0_p[2];
+	u32 reserved2[2];
+	u32 gpio1_p[4];
 	u32 reserved3[8];
 	u32 gpio0a_e;
 	u32 reserved4;
@@ -473,4 +477,43 @@ enum {
 
 };
 
+/* GRF_SOC_CON5 */
+enum {
+	RK3399_GMAC_PHY_INTF_SEL_SHIFT = 9,
+	RK3399_GMAC_PHY_INTF_SEL_MASK  = (7 << RK3399_GMAC_PHY_INTF_SEL_SHIFT),
+	RK3399_GMAC_PHY_INTF_SEL_RGMII = (1 << RK3399_GMAC_PHY_INTF_SEL_SHIFT),
+	RK3399_GMAC_PHY_INTF_SEL_RMII  = (4 << RK3399_GMAC_PHY_INTF_SEL_SHIFT),
+
+	RK3399_GMAC_CLK_SEL_SHIFT = 4,
+	RK3399_GMAC_CLK_SEL_MASK  = (3 << RK3399_GMAC_CLK_SEL_SHIFT),
+	RK3399_GMAC_CLK_SEL_125M  = (0 << RK3399_GMAC_CLK_SEL_SHIFT),
+	RK3399_GMAC_CLK_SEL_25M	  = (3 << RK3399_GMAC_CLK_SEL_SHIFT),
+	RK3399_GMAC_CLK_SEL_2_5M  = (2 << RK3399_GMAC_CLK_SEL_SHIFT),
+};
+
+/* GRF_SOC_CON6 */
+enum {
+	RK3399_RXCLK_DLY_ENA_GMAC_SHIFT = 15,
+	RK3399_RXCLK_DLY_ENA_GMAC_MASK =
+		(1 << RK3399_RXCLK_DLY_ENA_GMAC_SHIFT),
+	RK3399_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
+	RK3399_RXCLK_DLY_ENA_GMAC_ENABLE =
+		(1 << RK3399_RXCLK_DLY_ENA_GMAC_SHIFT),
+
+	RK3399_TXCLK_DLY_ENA_GMAC_SHIFT	= 7,
+	RK3399_TXCLK_DLY_ENA_GMAC_MASK =
+		(1 << RK3399_TXCLK_DLY_ENA_GMAC_SHIFT),
+	RK3399_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
+	RK3399_TXCLK_DLY_ENA_GMAC_ENABLE =
+		(1 << RK3399_TXCLK_DLY_ENA_GMAC_SHIFT),
+
+	RK3399_CLK_RX_DL_CFG_GMAC_SHIFT = 8,
+	RK3399_CLK_RX_DL_CFG_GMAC_MASK =
+		(0x7f << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT),
+
+	RK3399_CLK_TX_DL_CFG_GMAC_SHIFT = 0,
+	RK3399_CLK_TX_DL_CFG_GMAC_MASK =
+		(0x7f << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT),
+};
+
 #endif	/* __SOC_ROCKCHIP_RK3399_GRF_H__ */