ARM: atmel: add sama5d3xek support

Add sama5d3xek support with following feature
  - boot from NAND flash, PMECC support, 4bit ECC @ 512 bytes sector
  - boot from SPI flash support
  - boot from SD card support
  - LCD support
  - EMAC support
  - USB OHCI support

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>

5 files changed, 298 insertions, 0 deletions

diff --git a/arch/arm/include/asm/arch-at91/at91_dbu.h b/arch/arm/include/asm/arch-at91/at91_dbu.h
index 3429293535..9a640a5b04 100644
--- a/arch/arm/include/asm/arch-at91/at91_dbu.h
+++ b/arch/arm/include/asm/arch-at91/at91_dbu.h
@@ -38,4 +38,8 @@ typedef struct at91_dbu {
 #define AT91_DBU_CID_ARCH_9xx		0x01900000
 #define AT91_DBU_CID_ARCH_9XExx	0x02900000
 
+#define AT91_DBU_CIDR_MASK		0x1f
+#define AT91_DBU_CIDR			0x40
+#define AT91_DBU_EXID			0x44
+
 #endif
diff --git a/arch/arm/include/asm/arch-at91/clk.h b/arch/arm/include/asm/arch-at91/clk.h
index d4852a38c1..04b0f8322c 100644
--- a/arch/arm/include/asm/arch-at91/clk.h
+++ b/arch/arm/include/asm/arch-at91/clk.h
@@ -95,4 +95,5 @@ static inline unsigned long get_mci_clk_rate(void)
 }
 
 int at91_clock_init(unsigned long main_clock);
+void at91_periph_clk_enable(int id);
 #endif /* __ASM_ARM_ARCH_CLK_H__ */
diff --git a/arch/arm/include/asm/arch-at91/hardware.h b/arch/arm/include/asm/arch-at91/hardware.h
index 8812b1107b..b04641e014 100644
--- a/arch/arm/include/asm/arch-at91/hardware.h
+++ b/arch/arm/include/asm/arch-at91/hardware.h
@@ -43,6 +43,8 @@
 # include <asm/arch/at91cap9.h>
 #elif defined(CONFIG_AT91X40)
 # include <asm/arch/at91x40.h>
+#elif defined(CONFIG_SAMA5D3)
+# include <asm/arch/sama5d3.h>
 #else
 # error "Unsupported AT91 processor"
 #endif
diff --git a/arch/arm/include/asm/arch-at91/sama5d3.h b/arch/arm/include/asm/arch-at91/sama5d3.h
new file mode 100644
index 0000000000..883b932da7
--- /dev/null
+++ b/arch/arm/include/asm/arch-at91/sama5d3.h
@@ -0,0 +1,212 @@
+/*
+ * Chip-specific header file for the SAMA5D3 family
+ *
+ * (C) 2012 - 2013 Atmel Corporation.
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * Definitions for the SoC:
+ * SAMA5D3
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef SAMA5D3_H
+#define SAMA5D3_H
+
+/*
+ * defines to be used in other places
+ */
+#define CONFIG_ARMV7		/* ARM A5 Core */
+#define CONFIG_AT91FAMILY	/* it's a member of AT91 */
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define ATMEL_ID_FIQ	0	/* Advanced Interrupt Controller (FIQ) */
+#define ATMEL_ID_SYS	1	/* System Controller Interrupt */
+#define ATMEL_ID_DBGU	2	/* Debug Unit Interrupt */
+#define ATMEL_ID_PIT	3	/* Periodic Interval Timer Interrupt */
+#define ATMEL_ID_WDT	4	/* Watchdog timer Interrupt */
+#define ATMEL_ID_SMC	5	/* Multi-bit ECC Interrupt */
+#define ATMEL_ID_PIOA	6	/* Parallel I/O Controller A */
+#define ATMEL_ID_PIOB	7	/* Parallel I/O Controller B */
+#define ATMEL_ID_PIOC	8	/* Parallel I/O Controller C */
+#define ATMEL_ID_PIOD	9	/* Parallel I/O Controller D */
+#define ATMEL_ID_PIOE	10	/* Parallel I/O Controller E */
+#define ATMEL_ID_SMD	11	/* SMD Soft Modem */
+#define ATMEL_ID_USART0	12	/* USART 0 */
+#define ATMEL_ID_USART1	13	/* USART 1 */
+#define ATMEL_ID_USART2	14	/* USART 2 */
+#define ATMEL_ID_USART3	15	/* USART 3 */
+#define ATMEL_ID_UART0	16
+#define ATMEL_ID_UART1	17
+#define ATMEL_ID_TWI0	18	/* Two-Wire Interface 0 */
+#define ATMEL_ID_TWI1	19	/* Two-Wire Interface 1 */
+#define ATMEL_ID_TWI2	20	/* Two-Wire Interface 2 */
+#define ATMEL_ID_MCI0	21	/* High Speed Multimedia Card Interface 0 */
+#define ATMEL_ID_MCI1	22	/*  */
+#define ATMEL_ID_MCI2	23	/*  */
+#define ATMEL_ID_SPI0	24	/* Serial Peripheral Interface 0 */
+#define ATMEL_ID_SPI1	25	/* Serial Peripheral Interface 1 */
+#define ATMEL_ID_TC0	26	/* */
+#define ATMEL_ID_TC1	27	/* */
+#define ATMEL_ID_PWMC	28	/* Pulse Width Modulation Controller */
+#define ATMEL_ID_TSC	29	/* Touch Screen ADC Controller */
+#define ATMEL_ID_DMA0	30	/* DMA Controller */
+#define ATMEL_ID_DMA1	31	/* DMA Controller */
+#define ATMEL_ID_UHPHS	32	/* USB Host High Speed */
+#define ATMEL_ID_UDPHS	33	/* USB Device High Speed */
+#define ATMEL_ID_GMAC	34
+#define ATMEL_ID_EMAC	35	/* Ethernet MAC */
+#define ATMEL_ID_LCDC	36	/* LCD Controller */
+#define ATMEL_ID_ISI	37	/* Image Sensor Interface */
+#define ATMEL_ID_SSC0	38	/* Synchronous Serial Controller 0 */
+#define ATMEL_ID_SSC1	39	/* Synchronous Serial Controller 1 */
+#define ATMEL_ID_CAN0	40
+#define ATMEL_ID_CAN1	41
+#define ATMEL_ID_SHA	42
+#define ATMEL_ID_AES	43
+#define ATMEL_ID_TDES	44
+#define ATMEL_ID_TRNG	45
+#define ATMEL_ID_ARM	46
+#define ATMEL_ID_IRQ0	47	/* Advanced Interrupt Controller */
+#define ATMEL_ID_FUSE	48
+#define ATMEL_ID_MPDDRC	49
+
+/* sama5d3 series chip id definitions */
+#define ARCH_ID_SAMA5D3		0x8a5c07c0
+#define ARCH_EXID_SAMA5D31	0x00444300
+#define ARCH_EXID_SAMA5D33	0x00414300
+#define ARCH_EXID_SAMA5D34	0x00414301
+#define ARCH_EXID_SAMA5D35	0x00584300
+
+#define cpu_is_sama5d3()	(get_chip_id() == ARCH_ID_SAMA5D3)
+#define cpu_is_sama5d31()	(cpu_is_sama5d3() && \
+		(get_extension_chip_id() == ARCH_EXID_SAMA5D31))
+#define cpu_is_sama5d33()	(cpu_is_sama5d3() && \
+		(get_extension_chip_id() == ARCH_EXID_SAMA5D33))
+#define cpu_is_sama5d34()	(cpu_is_sama5d3() && \
+		(get_extension_chip_id() == ARCH_EXID_SAMA5D34))
+#define cpu_is_sama5d35()	(cpu_is_sama5d3() && \
+		(get_extension_chip_id() == ARCH_EXID_SAMA5D35))
+
+/*
+ * User Peripherals physical base addresses.
+ */
+#define ATMEL_BASE_MCI0		0xf0000000
+#define ATMEL_BASE_SPI0		0xf0004000
+#define ATMEL_BASE_SSC0		0xf000C000
+#define ATMEL_BASE_TC2		0xf0010000
+#define ATMEL_BASE_TWI0		0xf0014000
+#define ATMEL_BASE_TWI1		0xf0018000
+#define ATMEL_BASE_USART0	0xf001c000
+#define ATMEL_BASE_USART1	0xf0020000
+#define ATMEL_BASE_UART0	0xf0024000
+#define ATMEL_BASE_GMAC		0xf0028000
+#define ATMEL_BASE_PWMC		0xf002c000
+#define ATMEL_BASE_LCDC		0xf0030000
+#define ATMEL_BASE_ISI		0xf0034000
+#define ATMEL_BASE_SFR		0xf0038000
+/* Reserved: 0xf003c000 - 0xf8000000 */
+#define ATMEL_BASE_MCI1		0xf8000000
+#define ATMEL_BASE_MCI2		0xf8004000
+#define ATMEL_BASE_SPI1		0xf8008000
+#define ATMEL_BASE_SSC1		0xf800c000
+#define ATMEL_BASE_CAN1		0xf8010000
+#define ATMEL_BASE_TC3		0xf8014000
+#define ATMEL_BASE_TSADC	0xf8018000
+#define ATMEL_BASE_TWI2		0xf801c000
+#define ATMEL_BASE_USART2	0xf8020000
+#define ATMEL_BASE_USART3	0xf8024000
+#define ATMEL_BASE_UART1	0xf8028000
+#define ATMEL_BASE_EMAC		0xf802c000
+#define ATMEL_BASE_UDHPS	0xf8030000
+#define ATMEL_BASE_SHA		0xf8034000
+#define ATMEL_BASE_AES		0xf8038000
+#define ATMEL_BASE_TDES		0xf803c000
+#define ATMEL_BASE_TRNG		0xf8040000
+/* Reserved:	0xf804400 - 0xffffc00 */
+
+/*
+ * System Peripherals physical base addresses.
+ */
+#define ATMEL_BASE_SYS		0xffffc000
+#define ATMEL_BASE_SMC		0xffffc000
+#define ATMEL_BASE_PMECC	(ATMEL_BASE_SMC + 0x070)
+#define ATMEL_BASE_PMERRLOC	(ATMEL_BASE_SMC + 0x500)
+#define ATMEL_BASE_FUSE		0xffffe400
+#define ATMEL_BASE_DMAC0	0xffffe600
+#define ATMEL_BASE_DMAC1	0xffffe800
+#define ATMEL_BASE_MPDDRC	0xffffea00
+#define ATMEL_BASE_MATRIX	0xffffec00
+#define ATMEL_BASE_DBGU		0xffffee00
+#define ATMEL_BASE_AIC		0xfffff000
+#define ATMEL_BASE_PIOA		0xfffff200
+#define ATMEL_BASE_PIOB		0xfffff400
+#define ATMEL_BASE_PIOC		0xfffff600
+#define ATMEL_BASE_PIOD		0xfffff800
+#define ATMEL_BASE_PIOE		0xfffffa00
+#define ATMEL_BASE_PMC		0xfffffc00
+#define ATMEL_BASE_RSTC		0xfffffe00
+#define ATMEL_BASE_SHDWN	0xfffffe10
+#define ATMEL_BASE_PIT		0xfffffe30
+#define ATMEL_BASE_WDT		0xfffffe40
+#define ATMEL_BASE_SCKCR	0xfffffe50
+#define ATMEL_BASE_GPBR		0xfffffe60
+#define ATMEL_BASE_RTC		0xfffffeb0
+/* Reserved:	0xfffffee0 - 0xffffffff */
+
+/*
+ * Internal Memory.
+ */
+#define ATMEL_BASE_ROM		0x00100000	/* Internal ROM base address */
+#define ATMEL_BASE_SRAM		0x00200000	/* Internal ROM base address */
+#define ATMEL_BASE_SRAM0	0x00300000	/* Internal SRAM base address */
+#define ATMEL_BASE_SRAM1	0x00310000	/* Internal SRAM base address */
+#define ATMEL_BASE_SMD		0x00400000	/* Internal ROM base address */
+#define ATMEL_BASE_UDPHS_FIFO	0x00500000	/* USB Device HS controller */
+#define ATMEL_BASE_OHCI		0x00600000	/* USB Host controller (OHCI) */
+#define ATMEL_BASE_EHCI		0x00700000	/* USB Host controller (EHCI) */
+#define ATMEL_BASE_AXI		0x00800000	/* Video Decoder Controller */
+#define ATMEL_BASE_DAP		0x00900000	/* Video Decoder Controller */
+
+/*
+ * External memory
+ */
+#define ATMEL_BASE_CS0		0x10000000
+#define ATMEL_BASE_DDRCS	0x20000000
+#define ATMEL_BASE_CS1		0x40000000
+#define ATMEL_BASE_CS2		0x50000000
+#define ATMEL_BASE_CS3		0x60000000
+
+/*
+ * Other misc defines
+ */
+#define ATMEL_PIO_PORTS		5
+#define CPU_HAS_PIO3
+#define PIO_SCDR_DIV		0x3fff
+
+/*
+ * PMECC table in ROM
+ */
+#define ATMEL_PMECC_INDEX_OFFSET_512	0x10000
+#define ATMEL_PMECC_INDEX_OFFSET_1024	0x18000
+#define ATMEL_PMECC_ALPHA_OFFSET_512	0x10000
+#define ATMEL_PMECC_ALPHA_OFFSET_1024	0x18000
+
+/*
+ * SAMA5D3 specific prototypes
+ */
+#ifndef __ASSEMBLY__
+unsigned int get_chip_id(void);
+unsigned int get_extension_chip_id(void);
+unsigned int has_emac(void);
+unsigned int has_gmac(void);
+unsigned int has_lcdc(void);
+char *get_cpu_name(void);
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-at91/sama5d3_smc.h b/arch/arm/include/asm/arch-at91/sama5d3_smc.h
new file mode 100644
index 0000000000..eb53eba97f
--- /dev/null
+++ b/arch/arm/include/asm/arch-at91/sama5d3_smc.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2012 Atmel Corporation.
+ *
+ * Static Memory Controllers (SMC) - System peripherals registers.
+ * Based on SAMA5D3 datasheet.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef SAMA5D3_SMC_H
+#define SAMA5D3_SMC_H
+
+#ifdef __ASSEMBLY__
+#define AT91_ASM_SMC_SETUP0	(ATMEL_BASE_SMC + 0x600)
+#define AT91_ASM_SMC_PULSE0	(ATMEL_BASE_SMC + 0x604)
+#define AT91_ASM_SMC_CYCLE0	(ATMEL_BASE_SMC + 0x608)
+#define AT91_ASM_SMC_MODE0	(ATMEL_BASE_SMC + 0x60C)
+#else
+struct at91_cs {
+	u32	reserved[96];
+	u32	setup;		/* 0x600 SMC Setup Register */
+	u32	pulse;		/* 0x604 SMC Pulse Register */
+	u32	cycle;		/* 0x608 SMC Cycle Register */
+	u32	timings;	/* 0x60C SMC Cycle Register */
+	u32	mode;		/* 0x610 SMC Mode Register */
+};
+
+struct at91_smc {
+	struct at91_cs cs[4];
+};
+#endif /*  __ASSEMBLY__ */
+
+#define AT91_SMC_SETUP_NWE(x)		(x & 0x3f)
+#define AT91_SMC_SETUP_NCS_WR(x)	((x & 0x3f) << 8)
+#define AT91_SMC_SETUP_NRD(x)		((x & 0x3f) << 16)
+#define AT91_SMC_SETUP_NCS_RD(x)	((x & 0x3f) << 24)
+
+#define AT91_SMC_PULSE_NWE(x)		(x & 0x3f)
+#define AT91_SMC_PULSE_NCS_WR(x)	((x & 0x3f) << 8)
+#define AT91_SMC_PULSE_NRD(x)		((x & 0x3f) << 16)
+#define AT91_SMC_PULSE_NCS_RD(x)	((x & 0x3f) << 24)
+
+#define AT91_SMC_CYCLE_NWE(x)		(x & 0x1ff)
+#define AT91_SMC_CYCLE_NRD(x)		((x & 0x1ff) << 16)
+
+#define AT91_SMC_TIMINGS_TCLR(x)	(x & 0xf)
+#define AT91_SMC_TIMINGS_TADL(x)	((x & 0xf) << 4)
+#define AT91_SMC_TIMINGS_TAR(x)		((x & 0xf) << 8)
+#define AT91_SMC_TIMINGS_OCMS(x)	((x & 0x1) << 12)
+#define AT91_SMC_TIMINGS_TRR(x)		((x & 0xf) << 16)
+#define AT91_SMC_TIMINGS_TWB(x)		((x & 0xf) << 24)
+#define AT91_SMC_TIMINGS_RBNSEL(x)	((x & 0xf) << 28)
+#define AT91_SMC_TIMINGS_NFSEL(x)	((x & 0x1) << 31)
+
+#define AT91_SMC_MODE_RM_NCS		0x00000000
+#define AT91_SMC_MODE_RM_NRD		0x00000001
+#define AT91_SMC_MODE_WM_NCS		0x00000000
+#define AT91_SMC_MODE_WM_NWE		0x00000002
+
+#define AT91_SMC_MODE_EXNW_DISABLE	0x00000000
+#define AT91_SMC_MODE_EXNW_FROZEN	0x00000020
+#define AT91_SMC_MODE_EXNW_READY	0x00000030
+
+#define AT91_SMC_MODE_BAT		0x00000100
+#define AT91_SMC_MODE_DBW_8		0x00000000
+#define AT91_SMC_MODE_DBW_16		0x00001000
+#define AT91_SMC_MODE_DBW_32		0x00002000
+#define AT91_SMC_MODE_TDF_CYCLE(x)	((x & 0xf) << 16)
+#define AT91_SMC_MODE_TDF		0x00100000
+#define AT91_SMC_MODE_PMEN		0x01000000
+#define AT91_SMC_MODE_PS_4		0x00000000
+#define AT91_SMC_MODE_PS_8		0x10000000
+#define AT91_SMC_MODE_PS_16		0x20000000
+#define AT91_SMC_MODE_PS_32		0x30000000
+
+#endif