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authorTom Rini <trini@ti.com>2015-02-02 12:37:34 -0500
committerTom Rini <trini@ti.com>2015-02-02 12:37:34 -0500
commit37ffffb98d78c46c840fa6e3c835d915c4247827 (patch)
tree9ecc87c3bdb7b3c821798fee7ef64bf73a5e597f /arch/arm/include
parentade8bc14ad419f698406b162c9c5dfeee7406b4c (diff)
parentf3b4bc458de3285a04c5f60df6372ad5ca79fa60 (diff)
Merge branch 'master' of git://git.denx.de/u-boot-ti
Diffstat (limited to 'arch/arm/include')
-rw-r--r--arch/arm/include/asm/arch-omap3/mem.h43
-rw-r--r--arch/arm/include/asm/arch-omap3/mmc_host_def.h1
-rw-r--r--arch/arm/include/asm/arch-omap3/mux.h51
-rw-r--r--arch/arm/include/asm/arch-omap3/sys_proto.h1
-rw-r--r--arch/arm/include/asm/arch-omap5/clock.h20
5 files changed, 111 insertions, 5 deletions
diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h
index 0b78c1ca60..3ce270c5c9 100644
--- a/arch/arm/include/asm/arch-omap3/mem.h
+++ b/arch/arm/include/asm/arch-omap3/mem.h
@@ -249,6 +249,49 @@ enum {
#define MICRON_RASWIDTH_200 14
#define MICRON_V_MCFG_200(size) MCFG((size), MICRON_RASWIDTH_200)
+/* Samsung K4X51163PG - FGC6 (165MHz optimized) 6.06ns - from 2010.90 src */
+#define SAMSUNG_TDAL_165 5
+#define SAMSUNG_TDPL_165 2
+#define SAMSUNG_TRRD_165 2
+#define SAMSUNG_TRCD_165 3
+#define SAMSUNG_TRP_165 3
+#define SAMSUNG_TRAS_165 7
+#define SAMSUNG_TRC_165 10
+#define SAMSUNG_TRFC_165 12
+
+#define SAMSUNG_V_ACTIMA_165 \
+ ACTIM_CTRLA(SAMSUNG_TRFC_165, SAMSUNG_TRC_165, \
+ SAMSUNG_TRAS_165, SAMSUNG_TRP_165, \
+ SAMSUNG_TRCD_165, SAMSUNG_TRRD_165, \
+ SAMSUNG_TDPL_165, SAMSUNG_TDAL_165)
+
+#define SAMSUNG_TWTR_165 1
+#define SAMSUNG_TCKE_165 2
+#define SAMSUNG_XSR_165 20
+#define SAMSUNG_TXP_165 5
+
+#define SAMSUNG_V_ACTIMB_165 \
+ ACTIM_CTRLB(SAMSUNG_TWTR_165, SAMSUNG_TCKE_165, \
+ SAMSUNG_TXP_165, SAMSUNG_XSR_165)
+
+#define SAMSUNG_RASWIDTH_165 14
+#define SAMSUNG_V_MCFG_165(size) \
+ V_MCFG_RASWIDTH(SAMSUNG_RASWIDTH_165) | V_MCFG_CASWIDTH_10B | \
+ V_MCFG_ADDRMUXLEGACY_FLEX | V_MCFG_RAMSIZE(size) | \
+ V_MCFG_BANKALLOCATION_RBC | V_MCFG_RAMTYPE_DDR
+
+/* TODO: find which register these were taken from */
+
+#define SAMSUNG_BL_165 0x2
+#define SAMSUNG_SIL_165 0x0
+#define SAMSUNG_CASL_165 0x3
+#define SAMSUNG_WBST_165 0x0
+#define SAMSUNG_V_MR_165 ((SAMSUNG_WBST_165 << 9) | \
+ (SAMSUNG_CASL_165 << 4) | (SAMSUNG_SIL_165 << 3) | \
+ (SAMSUNG_BL_165))
+
+#define SAMSUNG_SHARING 0x00003700
+
/* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */
#define NUMONYX_TDAL_165 6 /* Twr/Tck + Trp/tck */
/* 15/6 + 18/6 = 5.5 -> 6 */
diff --git a/arch/arm/include/asm/arch-omap3/mmc_host_def.h b/arch/arm/include/asm/arch-omap3/mmc_host_def.h
index 0ba621a1b8..9f2896c4b9 100644
--- a/arch/arm/include/asm/arch-omap3/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-omap3/mmc_host_def.h
@@ -51,6 +51,7 @@ typedef struct t2 {
#define PBIASLITEPWRDNZ0 (1 << 1)
#define PBIASSPEEDCTRL0 (1 << 2)
#define PBIASLITEPWRDNZ1 (1 << 9)
+#define PBIASLITEVMODE0 (1 << 0)
#define CTLPROGIO1SPEEDCTRL (1 << 20)
diff --git a/arch/arm/include/asm/arch-omap3/mux.h b/arch/arm/include/asm/arch-omap3/mux.h
index eba4a5c7f0..3277b407d1 100644
--- a/arch/arm/include/asm/arch-omap3/mux.h
+++ b/arch/arm/include/asm/arch-omap3/mux.h
@@ -15,6 +15,12 @@
* PTU - Pull type Up
* DIS - Pull type selection is inactive
* EN - Pull type selection is active
+ * SB_LOW - Standby mode configuration: Output low-level
+ * SB_HI - Standby mode configuration: Output high-level
+ * SB_HIZ - Standby mode configuration: Output hi-impedence
+ * SB_PD - Standby mode pull-down enabled
+ * SB_PU - Standby mode pull-up enabled
+ * WKEN - Wakeup input enabled
* M0 - Mode 0
*/
@@ -26,6 +32,13 @@
#define EN (1 << 3)
#define DIS (0 << 3)
+#define SB_LOW (1 << 9)
+#define SB_HI (5 << 9)
+#define SB_HIZ (2 << 9)
+#define SB_PD (1 << 12)
+#define SB_PU (3 << 12)
+#define WKEN (1 << 14)
+
#define M0 0
#define M1 1
#define M2 2
@@ -36,8 +49,8 @@
#define M7 7
/*
- * To get the actual address the offset has to added
- * with OMAP34XX_CTRL_BASE to get the actual address
+ * To get the actual address the offset has to be added
+ * to OMAP34XX_CTRL_BASE
*/
/*SDRC*/
@@ -78,6 +91,33 @@
#define CONTROL_PADCONF_SDRC_DQS1 0x0074
#define CONTROL_PADCONF_SDRC_DQS2 0x0076
#define CONTROL_PADCONF_SDRC_DQS3 0x0078
+#define CONTROL_PADCONF_SDRC_BA0 0x05A0
+#define CONTROL_PADCONF_SDRC_BA1 0x05A2
+#define CONTROL_PADCONF_SDRC_A0 0x05A4
+#define CONTROL_PADCONF_SDRC_A1 0x05A6
+#define CONTROL_PADCONF_SDRC_A2 0x05A8
+#define CONTROL_PADCONF_SDRC_A3 0x05AA
+#define CONTROL_PADCONF_SDRC_A4 0x05AC
+#define CONTROL_PADCONF_SDRC_A5 0x05AE
+#define CONTROL_PADCONF_SDRC_A6 0x05B0
+#define CONTROL_PADCONF_SDRC_A7 0x05B2
+#define CONTROL_PADCONF_SDRC_A8 0x05B4
+#define CONTROL_PADCONF_SDRC_A9 0x05B6
+#define CONTROL_PADCONF_SDRC_A10 0x05B8
+#define CONTROL_PADCONF_SDRC_A11 0x05BA
+#define CONTROL_PADCONF_SDRC_A12 0x05BC
+#define CONTROL_PADCONF_SDRC_A13 0x05BE
+#define CONTROL_PADCONF_SDRC_A14 0x05C0
+#define CONTROL_PADCONF_SDRC_NCS0 0x05C2
+#define CONTROL_PADCONF_SDRC_NCS1 0x05C4
+#define CONTROL_PADCONF_SDRC_NCLK 0x05C6
+#define CONTROL_PADCONF_SDRC_NRAS 0x05C8
+#define CONTROL_PADCONF_SDRC_NCAS 0x05CA
+#define CONTROL_PADCONF_SDRC_NWE 0x05CC
+#define CONTROL_PADCONF_SDRC_DM0 0x05CE
+#define CONTROL_PADCONF_SDRC_DM1 0x05D0
+#define CONTROL_PADCONF_SDRC_DM2 0x05D2
+#define CONTROL_PADCONF_SDRC_DM3 0x05D4
/*GPMC*/
#define CONTROL_PADCONF_GPMC_A1 0x007A
#define CONTROL_PADCONF_GPMC_A2 0x007C
@@ -89,6 +129,7 @@
#define CONTROL_PADCONF_GPMC_A8 0x0088
#define CONTROL_PADCONF_GPMC_A9 0x008A
#define CONTROL_PADCONF_GPMC_A10 0x008C
+#define CONTROL_PADCONF_GPMC_A11 0x0264
#define CONTROL_PADCONF_GPMC_D0 0x008E
#define CONTROL_PADCONF_GPMC_D1 0x0090
#define CONTROL_PADCONF_GPMC_D2 0x0092
@@ -323,6 +364,8 @@
#define CONTROL_PADCONF_ETK_D13_ES2 0x05F6
#define CONTROL_PADCONF_ETK_D14_ES2 0x05F8
#define CONTROL_PADCONF_ETK_D15_ES2 0x05FA
+#define CONTROL_PADCONF_JTAG_RTCK 0x0A4E
+#define CONTROL_PADCONF_JTAG_TDO 0x0A50
/*Die to Die */
#define CONTROL_PADCONF_D2D_MCAD0 0x01E4
#define CONTROL_PADCONF_D2D_MCAD1 0x01E6
@@ -433,6 +476,10 @@
#define CONTROL_PADCONF_SYS_BOOT8 0x0226
/* AM/DM37xx specific */
+#define CONTROL_PADCONF_GPIO112 0x0134
+#define CONTROL_PADCONF_GPIO113 0x0136
+#define CONTROL_PADCONF_GPIO114 0x0138
+#define CONTROL_PADCONF_GPIO115 0x013A
#define CONTROL_PADCONF_GPIO127 0x0A54
#define CONTROL_PADCONF_GPIO126 0x0A56
#define CONTROL_PADCONF_GPIO128 0x0A58
diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h
index 34bd8c509a..bcf92fbe65 100644
--- a/arch/arm/include/asm/arch-omap3/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap3/sys_proto.h
@@ -23,6 +23,7 @@ struct emu_hal_params {
/* Board SDRC timing values */
struct board_sdrc_timings {
+ u32 sharing;
u32 mcfg;
u32 ctrla;
u32 ctrlb;
diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h
index 0dc584b8ce..f8e5630bcb 100644
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -236,13 +236,20 @@
#define VDD_MPU_ES2_LOW 880
#define VDD_MM_ES2_LOW 880
-/* TPS659038 Voltage settings in mv for OPP_NOMINAL */
-#define VDD_MPU_DRA752 1090
+/* DRA74x/75x voltage settings in mv for OPP_NOM per DM */
+#define VDD_MPU_DRA752 1100
#define VDD_EVE_DRA752 1060
#define VDD_GPU_DRA752 1060
-#define VDD_CORE_DRA752 1030
+#define VDD_CORE_DRA752 1060
#define VDD_IVA_DRA752 1060
+/* DRA72x voltage settings in mv for OPP_NOM per DM */
+#define VDD_MPU_DRA72x 1100
+#define VDD_EVE_DRA72x 1060
+#define VDD_GPU_DRA72x 1060
+#define VDD_CORE_DRA72x 1060
+#define VDD_IVA_DRA72x 1060
+
/* Efuse register offsets for DRA7xx platform */
#define DRA752_EFUSE_BASE 0x4A002000
#define DRA752_EFUSE_REGBITS 16
@@ -284,6 +291,13 @@
#define TPS659038_REG_ADDR_SMPS7 0x33
#define TPS659038_REG_ADDR_SMPS8 0x37
+/* TPS65917 */
+#define TPS65917_I2C_SLAVE_ADDR 0x58
+#define TPS65917_REG_ADDR_SMPS1 0x23
+#define TPS65917_REG_ADDR_SMPS2 0x27
+#define TPS65917_REG_ADDR_SMPS3 0x2F
+
+
/* TPS */
#define TPS62361_I2C_SLAVE_ADDR 0x60
#define TPS62361_REG_ADDR_SET0 0x0