diff options
| author | Anton Staaf <robotboy@chromium.org> | 2011-10-17 16:46:03 -0700 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2011-10-23 20:50:42 +0200 |
| commit | 44d6cbb6a77665caa14be2a561c4148446b3ba7e (patch) | |
| tree | 13f292cd04ea551b7cb26ed56ffa005c8ea0a123 /arch/arm/include | |
| parent | f8df9d0d1a1f668cfb37c02fa42e5fa10e0eec0f (diff) | |
arm: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/cache.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index d0518be28c..eef6a5a8f2 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -42,4 +42,15 @@ static inline void invalidate_l2_cache(void) void l2_cache_enable(void); void l2_cache_disable(void); +/* + * The current upper bound for ARM L1 data cache line sizes is 64 bytes. We + * use that value for aligning DMA buffers unless the board config has specified + * an alternate cache line size. + */ +#ifdef CONFIG_SYS_CACHELINE_SIZE +#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE +#else +#define ARCH_DMA_MINALIGN 64 +#endif + #endif /* _ASM_CACHE_H */ |