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authorHeiko Schocher <hs@denx.de>2014-10-31 08:31:04 +0100
committerTom Rini <trini@ti.com>2014-11-17 08:47:17 -0500
commit5abc00d02082056765a8029675e7b05ab6c35263 (patch)
tree381ca30258c8bcc82372e99ba2f903b9a74492c7 /arch/arm/include
parent667af36905157b65fd79493e7f821db606ebbd33 (diff)
arm, spl, at91: add at91sam9260 and at91sam9g45 spl support
add support for using spl code on at91sam9260 and at91sam9g45 based boards. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Bo Shen <voice.shen@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> [adopt Bo's change in spl.c] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Diffstat (limited to 'arch/arm/include')
-rw-r--r--arch/arm/include/asm/arch-at91/at91_common.h6
-rw-r--r--arch/arm/include/asm/arch-at91/at91_pmc.h1
-rw-r--r--arch/arm/include/asm/arch-at91/at91sam9260.h1
-rw-r--r--arch/arm/include/asm/arch-at91/at91sam9260_matrix.h5
-rw-r--r--arch/arm/include/asm/arch-at91/at91sam9_sdramc.h22
5 files changed, 34 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-at91/at91_common.h b/arch/arm/include/asm/arch-at91/at91_common.h
index 59e2f4391c..912e55c8de 100644
--- a/arch/arm/include/asm/arch-at91/at91_common.h
+++ b/arch/arm/include/asm/arch-at91/at91_common.h
@@ -23,9 +23,15 @@ void at91_udp_hw_init(void);
void at91_uhp_hw_init(void);
void at91_lcd_hw_init(void);
void at91_plla_init(u32 pllar);
+void at91_pllb_init(u32 pllar);
void at91_mck_init(u32 mckr);
void at91_pmc_init(void);
void mem_init(void);
void at91_phy_reset(void);
+void at91_sdram_hw_init(void);
+void at91_mck_init(u32 mckr);
+void at91_spl_board_init(void);
+void at91_disable_wdt(void);
+void matrix_init(void);
#endif /* AT91_COMMON_H */
diff --git a/arch/arm/include/asm/arch-at91/at91_pmc.h b/arch/arm/include/asm/arch-at91/at91_pmc.h
index 27331ff2d1..e206b55b1f 100644
--- a/arch/arm/include/asm/arch-at91/at91_pmc.h
+++ b/arch/arm/include/asm/arch-at91/at91_pmc.h
@@ -133,6 +133,7 @@ typedef struct at91_pmc {
#define AT91_PMC_MCKR_MDIV_MASK 0x00000300
#endif
+#define AT91_PMC_MCKR_PLLADIV_MASK 0x00003000
#define AT91_PMC_MCKR_PLLADIV_1 0x00000000
#define AT91_PMC_MCKR_PLLADIV_2 0x00001000
diff --git a/arch/arm/include/asm/arch-at91/at91sam9260.h b/arch/arm/include/asm/arch-at91/at91sam9260.h
index 2e902eef3e..1e613fa636 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9260.h
+++ b/arch/arm/include/asm/arch-at91/at91sam9260.h
@@ -95,6 +95,7 @@
#define ATMEL_BASE_SDRAMC 0xffffea00
#define ATMEL_BASE_SMC 0xffffec00
#define ATMEL_BASE_MATRIX 0xffffee00
+#define ATMEL_BASE_CCFG 0xffffef14
#define ATMEL_BASE_AIC 0xfffff000
#define ATMEL_BASE_DBGU 0xfffff200
#define ATMEL_BASE_PIOA 0xfffff400
diff --git a/arch/arm/include/asm/arch-at91/at91sam9260_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9260_matrix.h
index 4755fa10bb..dc61f48f52 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9260_matrix.h
+++ b/arch/arm/include/asm/arch-at91/at91sam9260_matrix.h
@@ -61,5 +61,10 @@ struct at91_matrix {
#define AT91_MATRIX_DBPUC (1 << 8)
#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
+#define AT91_MATRIX_EBI_IOSR_SEL (1 << 17)
+
+/* Maximum Number of Allowed Cycles for a Burst */
+#define AT91_MATRIX_SLOT_CYCLE (0xff << 0)
+#define AT91_MATRIX_SLOT_CYCLE_(x) (x << 0)
#endif
diff --git a/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h b/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h
index 5c98cc70d3..3a076c6b80 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h
+++ b/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h
@@ -25,6 +25,21 @@
#define AT91_ASM_SDRAMC_CR (ATMEL_BASE_SDRAMC + 0x08)
#define AT91_ASM_SDRAMC_MDR (ATMEL_BASE_SDRAMC + 0x24)
+#else
+struct sdramc_reg {
+ u32 mr;
+ u32 tr;
+ u32 cr;
+ u32 lpr;
+ u32 ier;
+ u32 idr;
+ u32 imr;
+ u32 isr;
+ u32 mdr;
+};
+
+int sdramc_initialize(unsigned int sdram_address,
+ const struct sdramc_reg *p);
#endif
/* SDRAM Controller (SDRAMC) registers */
@@ -62,11 +77,17 @@
#define AT91_SDRAMC_DBW_32 (0 << 7)
#define AT91_SDRAMC_DBW_16 (1 << 7)
#define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */
+#define AT91_SDRAMC_TWR_VAL(x) (x << 8)
#define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */
+#define AT91_SDRAMC_TRC_VAL(x) (x << 12)
#define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */
+#define AT91_SDRAMC_TRP_VAL(x) (x << 16)
#define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */
+#define AT91_SDRAMC_TRCD_VAL(x) (x << 20)
#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */
+#define AT91_SDRAMC_TRAS_VAL(x) (x << 24)
#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
+#define AT91_SDRAMC_TXSR_VAL(x) (x << 28)
#define AT91_SDRAMC_LPR (ATMEL_BASE_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */
#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */
@@ -93,5 +114,4 @@
#define AT91_SDRAMC_MD_SDRAM 0
#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1
-
#endif